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CY62256NLL-55SNXE Datasheet(PDF) 3 Page - Cypress Semiconductor |
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CY62256NLL-55SNXE Datasheet(HTML) 3 Page - Cypress Semiconductor |
3 / 16 page CY62256N Document Number: 001-06511 Rev. *F Page 3 of 16 Pin Configurations Figure 1. 28-pin DIP and Narrow SOIC Figure 2. 28-pin TSOP I and Reverse TSOP I Product Portfolio Product VCC Range (V) Speed (ns) Power Dissipation Operating, ICC (mA) Standby, ISB2 (μA) Min Typ[1] Max Typ[1] Max Typ[1] Max CY62256NLL Commercial 4.5 5.0 5.5 70 25 50 0.1 5 CY62256NLL Industrial 55/70 25 50 0.1 10 CY62256NLL Automotive-A 55/70 25 50 0.1 10 CY62256NLL Automotive-E 55 25 50 0.1 15 Table 1. Pin Definitions Pin Number Type Description 1–10, 21, 23–26 Input A0–A14. Address Inputs 11–13, 15–19, Input/Output I/O0–I/O7. Data lines. Used as input or output lines depending on operation 27 Input/Control WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is conducted 20 Input/Control CE. When LOW, selects the chip. When HIGH, deselects the chip 22 Input/Control OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins 14 Ground GND. Ground for the device 28 Power Supply VCC. Power supply for the device Note 1. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions (TA = 25 °C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested. |
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