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CY8CTMG200-16LGXI Datasheet(PDF) 5 Page - Cypress Semiconductor |
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CY8CTMG200-16LGXI Datasheet(HTML) 5 Page - Cypress Semiconductor |
5 / 309 page 5 Contents Section A: Overview 13 1. Pin Information 19 1.1 Pinouts....................................................................................................................................19 1.1.1 CY8CTMG200-16LGXI, CY8CTMG200A-16LGXI, CY8CTST200-16LGXI, CY8CTST200A-16LGXI PSoC 16-Pin Part Pinout 19 1.1.2 CY8CTMG200-24LQXI, CY8CTMG200A-24LQXI, CY8CTST200-24LQXI, CY8CTST200A-24LQXI PSoC 24-Pin Part Pinout 20 1.1.3 CY8CTMG200-32LQXI, CY8CTMG200A-32LQXI, CY8CTST200-32LQXI, CY8CTST200A-32LQXI, CY8CTMG201-32LQXI, CY8CTMG201A-32LQXI PSoC 32- Pin Part Pinout21 1.1.4 CY8CTMG200-48LTXI, CY8CTMG200A-48LTXI, CY8CTST200-48LTXI, CY8CTST200A-48LTXI, CY8CTMG201-48LTXI, CY8CTMG201A-48LTXI PSoC 48-Pin Part Pinout22 Section B: PSoC Core 23 2. CPU Core (M8C) 27 2.1 Overview.................................................................................................................................27 2.2 Internal Registers....................................................................................................................27 2.3 Address Spaces......................................................................................................................27 2.4 Instruction Set Summary ........................................................................................................28 2.5 Instruction Formats .................................................................................................................30 2.5.1 One-Byte Instructions ................................................................................................30 2.5.2 Two-Byte Instructions ................................................................................................30 2.5.3 Three-Byte Instructions..............................................................................................31 2.6 Register Definitions.................................................................................................................32 2.6.1 CPU_F Register ........................................................................................................32 2.6.2 Related Registers ......................................................................................................32 3. Supervisory ROM (SROM) 33 3.1 Architectural Description.........................................................................................................33 3.1.1 Additional SROM Feature..........................................................................................34 3.1.2 SROM Function Descriptions ....................................................................................34 3.1.2.1 SWBootReset Function ...............................................................................34 3.1.2.2 ReadBlock Function ....................................................................................35 3.1.2.3 WriteBlock Function.....................................................................................35 3.1.2.4 EraseBlock Function....................................................................................36 3.1.2.5 ProtectBlock Function..................................................................................36 3.1.2.6 TableRead Function ....................................................................................36 3.1.2.7 EraseAll Function ........................................................................................36 3.1.2.8 Checksum Function.....................................................................................37 3.1.2.9 Calibrate0 Function .....................................................................................37 3.1.2.10 Calibrate1 Function .....................................................................................37 [+] Feedback |
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