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LTC485CN8 Datasheet(PDF) 9 Page - Linear Technology |
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LTC485CN8 Datasheet(HTML) 9 Page - Linear Technology |
9 / 14 page LTC485 9 485fi applicaTions inForMaTion The LTC485 output stage will maintain a high impedance state until the breakdown of the N-channel or P-channel is reached when going positive or negative respectively. The output will be clamped to either VCC or ground by a Zener voltage plus a Schottky diode drop, but this voltage is way beyond the RS485 operating range. This clamp protects the MOS gates from ESD voltages well over 2000V. Because the ESD injected current in the N-well or substrateconsistsofmajoritycarriers,latchupisprevented by careful layout techniques. Propagation Delay Many digital encoding schemes are dependent upon the difference in the propagation delay times of the driver and the receiver. Using the test circuit of Figure 13, Figures 11 and12showthetypicalLTC485receiverpropagationdelay. The receiver delay times are: |tPLH – tPHL| = 9ns Typ, VCC = 5V The driver skew times are: Skew = 5ns Typ, VCC = 5V 10ns Max, VCC = 5V, TA = –40°C to 85°C Figure 11. Receiver tPHL 485 F11 DRIVER OUTPUTS RECEIVER OUTPUTS A B RO Figure 12. Receiver tPLH 485 F12 DRIVER OUTPUTS RECEIVER OUTPUTS A B RO Figure 13. Receiver Propagation Delay Test Circuit D R RECEIVER OUT R 100 100pF 100pF TTL IN tr, tf < 6ns BR 485 F13 |
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