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ATV750BL-25SC Datasheet(PDF) 10 Page - ATMEL Corporation |
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ATV750BL-25SC Datasheet(HTML) 10 Page - ATMEL Corporation |
10 / 16 page ATV750B 10 Using the ATV750B’s Many Advanced Features The ATV750B’s advanced flexibility packs more usable gates into 24-pins than any other logic device. The ATV750Bs start with the popular 22V10 architecture, and add several enhanced features: • Selectable D- and T-Type Registers - Each ATV750B flip-flop can be individually configured as either D- or T-type. Using the T-type configuration, JK and SR flip-flops are also easily created. These options allow more efficient product term usage. • Selectable Asynchronous Clocks - Each of the ATV750B’s flip-flops may be clocked by its own clock product term or directly from Pin 1 (SMD Lead 2). This removes the constraint that all registers must use the same clock. Buried state machines, counters and registers can all coexist in one device while running on separate clocks. Individual flip-flop clock source selection further allows mixing higher performance pin clocking and flexible product term clocking within one design. • A Full Bank of Ten More Registers - The ATV750B provides two flip-flops per output logic cell for a total of 20. Each register has its own sum term, its own reset term and its own clock term. • Independent I/O Pin and Feedback Paths - Each I/O pin on the ATV750B has a dedicated input path. Each of the 20 registers has its own feedback terms into the array as well. This feature, combined with individual product terms for each I/O’s output enable, facilitates true bi-directional I/O design. Programming Software Support As with all other Atmel PLDs, several third party develop- ment software products support the ATV750Bs. Several third party programmers support the ATV750B as well. Additionally, the ATV750B may be programmed to perform the ATV750/L’s functional subset (no T-type flip-flops or pin clocking) using the ATV750/L JEDEC file. In this case, the ATV750B becomes a direct replacement or speed upgrade for the ATV750/L. The ATV750/L programming algorithm is different from the ATV750B algorithm. Choose the appro- priate device in your programmer menu to ensure proper programming. Please refer to the Programmable Logic Development Tools section for a complete PLD software and programmer listing. Synchronous Preset and Asynchronous Reset One synchronous preset line is provided for all 20 registers in the ATV750B. The appropriate input signals to cause the internal clocks to go to a high state must be received during a synchronous preset. Appropriate setup and hold times must be met, as shown in the switching waveform diagram. An individual asynchronous reset line is provided for each of the 20 flip-flops. Both master and slave halves of the flip- flops are reset when the input signals received force the internal resets high. Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATV750B fuse patterns. Once the security fuse is programmed, all fuses will appear programmed during ver- ify. The security fuse should be programmed last, as its effect is immediate. Erasure Characteristics The entire memory array of an ATV750B is erased after exposure to ultraviolet light at a wavelength of 2537 Å. Complete erasure is assured after a minimum of 20 min- utes exposure using 12,000 µW/cm2 intensity lamps spaced one inch away from the chip. Minimum erase time for lamps at other intensity ratings can be calculated from the minimum integrated erasure dose of 15 W•sec/cm 2. To prevent unintentional erasure, an opaque label is recom- mended to cover the clear window on any UV erasable PLD which will be subjected to continuous fluorescent indoor lighting or sunlight. Atmel CMOS PLDs The ATV750B utilizes an advanced 0.65-micron CMOS EPROM technology. This technology’s state of the art fea- tures are the optimum combination for PLDs: • CMOS technology provides high speed, low power, and high noise immunity. • EPROM technology is the most cost effective method for producing PLDs - surpassing bipolar fusible link technology in low cost, while providing the necessary reprogrammability. • EPROM reprogrammability, which is 100% tested before shipment, provides inherently better programmability and reliability than one-time fusible PLDs. |
Similar Part No. - ATV750BL-25SC |
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Similar Description - ATV750BL-25SC |
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