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ATV750L-25JC Datasheet(PDF) 8 Page - ATMEL Corporation |
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ATV750L-25JC Datasheet(HTML) 8 Page - ATMEL Corporation |
8 / 14 page ATV750/L 8 Preload of Registered Outputs The ATV750's registers are provided with circuitry to allow loading of each register asynchronously with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A VIH level on the I/O pin will force the register high; a VIL will force it low, independent of the output polarity. The pre- load state is entered by placing an 10.5V to 11.5V signal on pin 8 on DIPs, and pin 10 on SMPs. When the clock term is pulsed high, the data on the I/O pin is placed into the regis- ter chosen by the Select Pin. Power-Up Reset The registers in the ATV750(L) are designed to reset dur- ing power up. At a point delayed slightly from V CC crossing 3.8V, all registers will be reset to the low state. The output state will depend on the polarity of the output buffer. This feature is critical for state machine initialization. How- ever, due to the asynchronous nature of reset and the uncertainty of how V CC actually rises in the system, the fol- lowing conditions are required: 1. The V CC rise must be monotonic, 2. After reset occurs, all input and feedback setup times must be met before driving the clock term high, and 3. The signals from which the clock is derived must remain stable during t PR. Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. Level forced on registered output pin during PRELOAD cycle Select Pin State Register #1 state after cycle Register#2 State after cycle V IH Low High X V IL Low Low X V IH High X High V IL High X Low Parameter Description Min Typ Max Units t PR Power-Up Reset Time 600 1000 ns Pin Capacitance (f = 1 MHz, T = 25 °C)(1) Typ Max Units Conditions C IN 58 pF V IN = 0V C OUT 68 pF V OUT = 0V |
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