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ATV2500BQ-25KC Datasheet(PDF) 9 Page - ATMEL Corporation |
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ATV2500BQ-25KC Datasheet(HTML) 9 Page - ATMEL Corporation |
9 / 18 page ATV2500B 9 AC Characteristics Symbol Parameter -12 -15 -20 -25 -30 Units Min Max Mi n Ma x Min Ma x Min Ma x Min Ma x t PD1 Input to Non-Registered Output 12 15 20 25 30 ns t PD2 Feedback to Non-Registered Output 12 15 20 25 30 ns t PD3 Input to Non-Registered Feedback 8 11 151820 ns t PD4 Feedback to Non-Registered Feedback 8 11 151820 ns t EA1 Input to Output Enable 12 15 20 25 30 ns t ER1 Input to Output Disable 12 15 20 25 30 ns t EA2 Feedback to Output Enable 12 15 20 25 30 ns t ER2 Feedback to Output Disable 12 15 20 25 30 ns t AW Asynchronous Reset Width 6 8 12 15 18 ns t AP Asynchronous Reset to Registered Output 15 18 22 28 30 ns t APF Asynchronous Reset to Registered Feedback 12 15 19 25 30 ns Input Test Waveforms and Measurement Levels Output Test Load Preload and Observability of Registered Outputs The ATV2500Bs registers are provided with circuitry to allow loading of each register asynchronously with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A V IH level on the odd I/O pins will force the appropriate register high; a V IL will force it low, independent of the polarity or other configuration bit settings. The PRELOAD state is entered by placing an 10.25V to 10.75V signal on SMP lead 42. When the preload clock SMP lead 23 is pulsed high, the data on the I/O pins is placed into the 12 registers chosen by the Q select and even/odd select pins. Register 2 observability mode is entered by placing an 10.25V to 10.75V signal on pin/lead 2. In this mode, the contents of the buried register bank will appear on the associated outputs when the OE control signals are active. |
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