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ATV2500BL-20KI Datasheet(PDF) 11 Page - ATMEL Corporation |
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ATV2500BL-20KI Datasheet(HTML) 11 Page - ATMEL Corporation |
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11 / 18 page  ATV2500B 11 Security Fuse Usage A single fuse is provided to prevent unauthorized copying of ATV2500B fuse patterns. Once programmed, the out- puts will read programmed during verify. The security fuse should be programmed last, as its effect is immediate. The security fuse also inhibits Preload and Q2 observabil- ity. Atmel CMOS PLDs The ATV2500Bs utilize an advanced 0.65-micron CMOS EPROM technology. This technology's state of the art fea- tures are the optimum combination for PLDs: • CMOS technology provides high speed, low power, and high noise immunity. • EPROM technology is the most cost effective method for producing PLDs - surpassing bipolar fusible link technology in low cost, while providing the necessary reprogrammability. • EPROM reprogrammability, which is 100% tested before shipment, provides inherently better programmability and reliability than one-time fusible PLDs. Using the ATV2500Bs Many Advanced Features The ATV2500Bs advanced flexibility packs more usable ga tes in to 4 4 le ads th an ot he r PLDs. Som e of th e ATV2500Bs key features are: • Fully Connected Logic Array - Each array input is always available to every product term. This makes logic placement a breeze. • Selectable D- and T-Type Registers - Each ATV2500B flip-flop can be individually configured as either D- or T-type. Using the T-type configuration, JK and SR flip-flops are also easily created. These options allow more efficient product term usage. • Buried Combinatorial Feedback - Each macrocell's Q2 register may be bypassed to feed its input (D/T2) directly back to the logic array. This provides further logic expansion capability without using precious pin resources. • Selectable Synchronous/Asynchronous Clocking - Each of the ATV2500Bs flip-flops has a dedicated clock product term. This removes the constraint that all registers use the same clock. Buried state machines, counters and registers can all coexist in one device while running on sep- arate clocks. Individual flip-flop clock source selection fur- ther allows mixing higher performance pin clocking and flexible product term clocking within one design. • A Total of 48 Registers - The ATV2500B provides two flip-flops per macrocell - a total of 48. Each register has its own clock and reset terms, as well as its own sum term. • Independent I/O Pin and Feedback Paths - Each I/O pin on the ATV2500B has a dedicated input path. Each of the 48 registers has its own feedback term into the array as well. These features, combined with individual product terms for each I/O's output enable, facilitate true bi- directional I/O design. • Combinable Sum Terms - Each output macrocell's three sum terms may be combined into a single term. This provides a fan in of up to 12 product terms per sum term with no speed penalty. Programming Software Support As with all other Atmel PLDs, several third party PLD devel- opment software products and programmers will support the ATV2500Bs. Se vera l t h ird p a rt y pro g ra mme rs w ill sup port t h e ATV2500B as well. Additionally, the ATV2500B may be programmed to perform the ATV2500H/Ls functional sub- set (no T-type flip-flops, pin clocking or D/T2 feedback) using the ATV2500H/L JEDEC file. In this case, the ATV2500B becomes a direct replacement or speed upgrade for the ATV2500H/L (additional GND connections are required). Please refer to the Programmable Logic Development Tools section for a complete PLD software and programmer listing. Erasure Characteristics The entire memory array of an ATV2500B is erased after exposure to ultraviolet light at a wavelength of 2537 Å. Complete erasure is assured after a minimum of 20 min- utes exposure using 12,000 µW/cm2 intensity lamps spaced one inch away from the chip. Minimum erase time for lamps at other intensity ratings can be calculated from the minimum integrated erasure dose of 15 W•sec/cm 2. To prevent unintentional erasure, an opaque label is recom- mended to cover the clear window on any UV erasable PLD which will be subjected to continuous fluorescent indoor lighting or sunlight. |
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