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AT6010A-2AC Datasheet(PDF) 2 Page - ATMEL Corporation |
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AT6010A-2AC Datasheet(HTML) 2 Page - ATMEL Corporation |
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2 / 28 page  AT6000(LV) Series 2 Devices range in size from 4,000 to 30,000 usable gates, and 1024 to 6400 registers. Pin locations are consistent throughout the AT6000 Series for easy design migration. High-I/O versions are available for the lower gate count devices. AT6000 Series FPGAs utilize a reliable 0.6 µm single-poly, double-metal CMOS process and are 100% factory-tested. Atmel's PC- and workstation-based Integrated Develop- ment System is used to create AT6000 Series designs. Multiple design entry methods are supported. The Atmel architecture was developed to provide the high- est levels of performance, functional density and design flexibility in an FPGA. The cells in the Atmel array are small, very efficient and contain the most important and most commonly used logic and wiring functions. The cell’s small size leads to arrays with large numbers of cells, greatly multiplying the functionality in each cell. A simple, high-speed busing network provides fast, efficient commu- nication over medium and long distances. The Symmetrical Array At the heart of the Atmel architecture is a symmetrical array of identical cells (Figure 1). The array is continuous and completely uninterrupted from one edge to the other, except fo r bus re pe at ers spaced every eight cells (Figure 2). In addition to logic and storage, cells can also be used as wires to connect functions together over short distances and are useful for routing in tight spaces. The Busing Network There are two kinds of buses: local and express (see Figures 2 and 3). Local buses are the link between the array of cells and the busing network. There are two local buses – North-South 1 and 2 (NS1 and NS2) – for every column of cells, and two local buses – East-West 1 and 2 (EW1 and EW2) – for every row of cells. In a sector (an 8 x 8 array of cells enclosed by repeaters) each local bus is connected to every cell in its column or row, thus providing every cell in the array with read/write access to two North-South and two East-West buses. Figure 1. Symmetrical Array Surrounded by I/O |
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