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ATMEGA163L-4AC Datasheet(PDF) 8 Page - ATMEL Corporation |
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ATMEGA163L-4AC Datasheet(HTML) 8 Page - ATMEL Corporation |
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8 / 187 page  8 ATmega163(L) 1142E–AVR–02/03 Figure 5. The ATmega163 AVR RISC Architecture The AVR uses a Harvard architecture concept – with separate memories and buses for program and data. The Program memory is executed with a two stage pipeline. While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept enables instructions to be executed in every clock cycle. The Program memory is In-System Re-programmable Flash memory. With the jump and call instructions, the whole 8K word address space is directly accessed. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot Program section (256 to 2,048 bytes, see page 134) and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section is allowed only in the Boot Program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The 11-bit Stack Pointer SP is read/write accessible in the I/O space. 8K X 16 Program Memory Instruction Register Instruction Decoder Program Counter Control Lines 32 x 8 General Purpose Registrers ALU Status and Control Interrupt Unit SPI Unit 8-bit Timer/Counter Watchdog Timer A/D Converter Analog Comparator 32 I/O Lines 512 x 8 EEPROM Data Bus 8-bit Two-wire Serial Interface 16-bit Timer/Counter with PWM 8-bit Timer/Counter with PWM 1024 x 8 Data SRAM Serial UART |
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