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ATMEGA163 Datasheet(PDF) 59 Page - ATMEL Corporation |
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ATMEGA163 Datasheet(HTML) 59 Page - ATMEL Corporation |
59 / 187 page 59 ATmega163(L) 1142E–AVR–02/03 on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. After wake-up, the MCU is halted for four clock cycles, it executes the interrupt routine, and resumes execution from the instruction following SLEEP. • During asynchronous operation, the synchronization of the interrupt flags for the asynchronous timer takes three processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the Interrupt Flag. The output compare pin is changed on the timer clock and is not synchronized to the processor clock. • After waking up from Power-save mode with the asynchronous timer enabled, there will be a short interval in which TCNT2 will read as the same value as before Power- save mode was entered. After an edge on the asynchronous clock, TCNT2 will read correctly (The compare and overflow functions of the Timer are not affected by this behavior.). Safe procedure to ensure that the correct value is read: 1. Write any value to either of the registers OCR2 or TCCR2. 2. Wait for the corresponding Update Busy Flag to be cleared. 3. Read TCNT2. Note that OCR2 and TCCR2 are never modified by hardware, and will always read correctly. |
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