ATF1500A/AL

11

Power Up Reset

The ATF1500A's registers are designed to reset during

the registered output state will always be low on power-up.

This feature is critical for state machine initialization. How-

ever, due to the asynchronous nature of reset and the

lowing conditions are required:

2. After reset occurs, all input and feedback setup times

must be met before driving the clock signal high, and

3. Signals from which clocks are derived must remain sta-

Power Down Mode

The ATF1500A includes an optional pin controlled power

down feature. When this mode is enabled, the PD pin acts

as the power down pin. When the PD pin is high, the device

supply current is reduced to less than 10

µA. During power

down, all output data and internal logic states are latched

and held. Therefore, all registered and combinatorial output

data remain valid. Any outputs which were in a HI-Z state at

the onset of power down will remain at HI-Z. During power

down, all input signals except the power down pin are

blocked. Input and I/O hold latches remain active to insure

that pins do not float to indeterminate levels, further reduc-

ing system power. The power down pin feature is enabled

in the logic design file. Designs using the power down pin

may not use the PD pin logic array input. However, all other

PD pin macrocell resources may still be used, including the

buried feedback and foldback product term array inputs.

Register Preload

The ATF1500A's registers are provided with circuitry to

allow loading of each register with either a high or a low.

This feature will simplify testing since any state can be

forced into the registers to control test sequencing. A

JEDEC file with preload is generated when a source file

with preload vectors is compiled. Once downloaded, the

JEDEC file preload sequence will be done automatically

when vectors are run by any approved programmers. The

preload mode is enabled by raising an input pin to a high

voltage level. Contact Atmel PLD Applications for PRE-

LOAD pin assignments, timing and voltage requirements.

Output Slew Rate Control

Each ATF1500A macrocell contains a configuration bit for

each I/O to control its output slew rate. This allows selected

data paths to operate at maximum throughput while reduc-

ing system noise from outputs that are not speed-critical.

Outputs default to slow edges, and may be individually set

to fast in the design file. Output transition times for outputs

Security Fuse Usage

A single fuse is provided to prevent unauthorized copying

of the ATF1500A fuse patterns. Once programmed, fuse

verify and preload are prohibited. However, the 160-bit

User Signature remains accessible.

The security fuse should be programmed last, as its effect

is immediate.

Parameter

Description

Typ

Max

Units

Power-Up

Reset Time

210

µs

Power-Up

Reset

Voltage

3.8

4.5

V