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SN74ALVCH16901DGGR Datasheet(PDF) 7 Page - Texas Instruments |
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SN74ALVCH16901DGGR Datasheet(HTML) 7 Page - Texas Instruments |
7 / 14 page SN74ALVCH16901 18BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS SCES010F − JULY 1995 − REVISED SEPTEMBER 2004 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 1.8 V VCC = 2.5 V ± 0.2 V VCC = 2.7 V VCC = 3.3 V ± 0.3 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX UNIT fclock Clock frequency † 125 125 125 MHz tw Pulse CLK ↑ † 3 3 3 ns tw Pulse duration LE high † 3 3 3 ns A, APAR or B, BPAR before CLK ↑ † 1.9 2 1.7 tsu Setup time CLKEN before CLK ↑ † 2.1 2.1 1.7 ns tsu Setup time A, APAR or B, BPAR before LE ↓ † 1.4 1.3 1.2 ns A, APAR or B, BPAR after CLK ↑ † 0.4 0.4 0.5 th Hold time CLKEN after CLK ↑ † 0.5 0.5 0.7 ns th Hold time A, APAR or B, BPAR after LE ↓ † 0.9 1.1 0.9 ns † This information was not available at the time of publication. |
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