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AT89C55WD-24JC Datasheet(PDF) 7 Page - ATMEL Corporation |
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AT89C55WD-24JC Datasheet(HTML) 7 Page - ATMEL Corporation |
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7 / 37 page  7 AT89C55WD 1921B–MICRO–09/02 Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register. Dual Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H- 83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The user should always initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register. Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to “1” during power up. It can be set and rest under software control and is not affected by reset. Table 2. T2CON—Timer/Counter 2 Control Register T2CON Address = 0C8H Reset Value = 0000 0000B Bit Addressable Bit TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 76543210 Table 3. AUXR: Auxiliary Register AUXR Address = 8EH Reset Value = XXX00XX0B Not Bit Addressable –– – WDIDLE DISRTO –– DISALE Bit 7 6 5 4 3 2 1 0 – Reserved for future expansion DISALE Disable/Enable ALE DISALE Operating Mode 0 ALE is emitted at a constant rate of 1/6 the oscillator frequency 1 ALE is active only during a MOVX or MOVC instruction DISRTO Disable/Enable Reset out DISRTO Operating Mode 0 Reset pin is driven High after WDT times out 1 Reset pin is input only WDIDLE Disable/Enable WDT in IDLE mode WDIDLE Operating Mode 0 WDT continues to count in IDLE mode 1 WDT halts counting in IDLE mode |
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