Not

5

Power Down Mode

In the power down mode the oscillator is stopped, and the

instruction that invokes power down is the last instruction

executed. The on-chip RAM and Special Function Regis-

ters retain their values until the power down mode is termi-

nated. The only exit from power down is a hardware reset.

Reset redefines the SFRs but does not change the on-chip

restored to its normal operating level and must be held

active long enough to allow the oscillator to restart and sta-

bilize.

Program Memory Lock Bits

On the chip are three lock bits which can be left unpro-

grammed (U) or can be programmed (P) to obtain the addi-

tional features listed in the table below:

When lock bit 1 is programmed, the logic level at the EA pin

is sampled and latched during reset. If the device is pow-

ered up without a reset, the latch initializes to a random

value, and holds that value until reset is activated. It is nec-

essary that the latched value of EA be in agreement with

the current logic level at that pin in order for the device to

function properly.

Lock Bit Protection Modes

Program Lock Bits

Protection Type

LB1

LB2

LB3

1

U

U

U

No program lock features.

2

P

U

U

MOVC instructions executed from external program memory are disabled from fetching code

bytes from internal memory, EA is sampled and latched on reset, and further programming of the

QuickFlash is disabled.

3

P

P

U

Same as mode 2, also verify is disabled.

4

P

P

P

Same as mode 3, also external execution is disabled.

Programming the QuickFlash

The AT87F51 is shipped with the on-chip QuickFlash mem-

ory array ready to be programmed. The programming inter-

face needs a high-voltage (12-volt) program enable signal

and is compatible with conventional third-party Flash or

EPROM programmers.

The AT87F51 code memory array is programmed byte-by-

byte.

Programming Algorithm: Before programming the

AT87F51, the address, data, and control signals should be

set up according to the QuickFlash programming mode

table and Figures 3 and 4. To program the AT87F51, take

the following steps:

1.

Input the desired memory location on the address

lines.

2.

Input the appropriate data byte on the data lines.

3.

Activate the correct combination of control signals.

4.

5.

Pulse ALE/PROG once to program a byte in the Quick-

Flash array or the lock bits. The byte-write cycle is self-

timed and typically takes no more than 1.5 ms. Repeat

steps 1 through 5, changing the address and data for

the entire array or until the end of the object file is

reached.

Data Polling: The AT87F51 features Data Polling to indi-

cate the end of a write cycle. During a write cycle, an

attempted read of the last byte written will result in the com-

plement of the written datum on PO.7. Once the write cycle

has been completed, true data are valid on all outputs, and

the next cycle may begin. Data Polling may begin any time

after a write cycle has been initiated.

Ready/Busy: The progress of byte programming can also

be monitored by the RDY/BSY output signal. P3.4 is pulled

low after ALE goes high during programming to indicate

BUSY. P3.4 is pulled high again when programming is

done to indicate READY.

Program Verify: If lock bits LB1 and LB2 have not been

programmed, the programmed code data can be read back

via the address and data lines for verification. The lock bits

cannot be verified directly. Verification of the lock bits is

achieved by observing that their features are enabled.

Reading the Signature Bytes: The signature bytes are

read by the same procedure as a normal verification of

locations 030H, 031H, and 032H, except that P3.6 and

P3.7 must be pulled to a logic low. The values returned are

as follows.

(030H) = 1EH indicates manufactured by Atmel

(031H) = 87H indicates 87F family

(032H) = 01H indicates 87F51