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AT49BV1614T-12CI Datasheet(PDF) 3 Page - ATMEL Corporation |
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AT49BV1614T-12CI Datasheet(HTML) 3 Page - ATMEL Corporation |
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3 / 18 page  AT49BV16X4(T) 3 A six byte command (bypass unlock) sequence to remove the requirement of entering the three byte program sequence is offered to further improve programming time. After entering the six byte code, only single pulses on the write control lines are required for writing into the device. This mode (single pulse byte/word program) is exited by powering down the device, or by pulsing the RESET pin low and then bringing it back to VCC. Erase and Erase Sus- pend/Resume commands will not work while in this mode; if entered they will result in data being programmed into the device. It is not recommended that the six byte code reside in the software of the final product but only exist in external programming code. The BYTE pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE pin is set at logic “1”, the device is in word configuration, I/O0- I/O15 are active and controlled by CE and OE. If the BYTE pin is set at logic “0”, the device is in byte con- figuration, and only data I/O pins I/O0-I/O7 are active and controlled by CE and OE. The data I/O pins I/O8-I/O14 are tri-stated, and the I/O15 pin is used as an input for the LSB (A-1) address function. Block Diagram Device Operation READ: The AT49BV16X4(T) is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins are asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus conten- tion. COMMAND SEQUENCES: When the device is first pow- ered on it will be reset to the read or standby mode depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the Command Definitions table (I/O8 - I/O15 are don't care inputs for the command codes). The command sequences are written by applying a low pulse on the WE or CE input with CE or WE low (respec- tively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Standard microprocessor write timings are used. The address loca- tions used in the command sequences are not affected by entering the command sequences. IDENTIFIER REGISTER STATUS REGISTER DATA COMPARATOR OUTPUT BUFFER INPUT BUFFER COMMAND REGISTER Y-GATING WRITE STATE MACHINE PROGRAM/ERASE VOLTAGE SWITCH CE WE OE RESET BYTE RDY/BUSY VPP VCC GND Y-DECODER X-DECODER INPUT BUFFER ADDRESS LATCH I/O0 - I/O15/A-1 A0 - A19 PLANE B SECTORS PLANE A SECTORS |
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