DAC8143

–6–

REV. C

DEFINITION OF SPECIFICATIONS

RESOLUTION

The resolution of a DAC is the number of states (2

the full-scale range (FSR) is divided (or resolved), where “n” is

equal to the number of bits.

SETTLING TIME

Time required for the analog output of the DAC to settle to

within 1/2 LSB of its final value for a given digital input stimu-

lus; i.e., zero to full-scale.

GAIN

Ratio of the DAC’s external operational amplifier output voltage

FEEDTHROUGH ERROR

Feedthrough error limits are specified with all switches off.

OUTPUT CAPACITANCE

OUTPUT LEAKAGE CURRENT

GENERAL CIRCUIT INFORMATION

The DAC8143 is a 12-bit serial-input, buffered serial-output,

multiplying CMOS D/A converter. It has an R-2R resistor lad-

der network, a 12-bit input shift register, 12-bit DAC register,

control logic circuitry, and a buffered digital output stage.

The control logic forms an interface in which serial data is

loaded, under microprocessor control, into the input shift regis-

ter and then transferred, in parallel, to the DAC register. In

addition, buffered serial output data is present at the SRO pin

when input data is loaded into the input register. This buffered

data follows the digital input data (SRI) by 12 clock cycles and

is available for daisy-chaining additional DACs.

An asynchronous CLEAR function allows resetting the DAC

register to a zero code (0000 0000 0000) without altering data

stored in the registers.

A simplified circuit of the DAC8143 is shown in Figure 10. An

inversed R-2R ladder network consisting of silicon-chrome,

thin-film resistors, and twelve pairs of NMOS current-steering

switches. These switches steer binarily weighted currents into

a constant current in each ladder leg, regardless of digital input

code. This constant current results in a constant input resis-

Ω). The V

be driven by any reference voltage or current, ac or dc, that is

within the limits stated in the Absolute Maximum Ratings chart.

The twelve output current-steering switches are in series with

the R-2R resistor ladder, and therefore, can introduce bit errors.

It was essential to design these switches such that the switch

“ON” resistance be binarily scaled so that the voltage drop

across each switch remains constant. If, for example, Switch 1

of Figure 10 was designed with an “ON” resistance of 10

Ω,

Switch 2 for 20

Ω, etc., a constant 5 mV drop would then be

maintained across each switch.

To further ensure accuracy across the full temperature range,

permanently “ON” MOS switches were included in series with

the feedback resistor and the R-2R ladder’s terminating resistor.

The Simplified DAC Circuit, Figure 10, shows the location of

these switches. These series switches are equivalently scaled to

two times Switch 1 (MSB) and top Switch 12 (LSB) to main-

tain constant relative voltage drops with varying temperature.

series switches.

10k

10k

10k

20k

20k

20k

20k

20k

10k

BIT 1 (MSB)

BIT 12 (LSB)

BIT 3

BIT 2

DIGITAL INPUTS

(SWITCHES SHOWN FOR DIGITAL INPUTS "HIGH")

*

*

PERMANENTLY "ON"

Figure 10. Simplified DAC Circuit