DAC8143

–8–

REV. C

Ω for any single bit of Logic 1.

Therefore, the offset gain varies as follows:

at code 0011 1111 1111,

10 k

Ω

10 k

Ω







at code 0100 0000 0000,

10 k

Ω

30 k

Ω







using either the amplifier’s pulling pins, an external pulling

OP27, and OP42.

INTERFACE LOGIC OPERATION

The microprocessor interface of the DAC8143 has been design-

ed with multiple STROBE and LOAD inputs to maximize inter-

facing options. Control signals decoding may be done on chip or

with the use of external decoding circuitry (see Figure 21).

Serial data is clocked into the input register and buffered output

on the rising edge.

STB3 may be used with a falling edge clock

data.

WORD N

WORD N –1

WORD N –2

WORD N –1

WORD N

BIT 11

BIT 2

BIT 12

LSB

BIT 1

MSB

BIT 12

LSB

BIT 2

BIT 1

MSB

SRI

BIT 2

BIT 1

MSB

BIT 1

MSB

BIT 2

BIT 12

LSB

BIT 1

LSB

t

SRO

t

t

PD

t

STB1

t

STB2

t

STB3

t

STB4

12

12

1

2

t

LD1

t

LD2

t

SR1

12

11

t

ASB

LOAD NEW 12-BIT WORD INTO

INPUT REGISTER AND SHIFT

OUT PREVIOUS WORD

LOAD INPUT REGISTER'S

DATA INTO DAC REGISTER

NOTES:

STB

BITS INTO INPUT REGISTER.

THE INPUT SHIFT REGISTER MSB FIRST.

Figure 15. Timing Diagram

Serial data output (SRO) follows the serial data input (SRI) by

12 clocked bits.

prevent any further data input.

When a new data word has been entered into the input register,

it is transferred to the DAC register by asserting both LOAD

inputs.

The

CLR input allows asynchronous resetting of the DAC regis-

ter to 0000 0000 0000. This reset does not affect data held in

the input registers. While in unipolar mode, a CLEAR will

result in the analog output going to 0 V. In bipolar mode, the

INTERFACE INPUT DESCRIPTION

and Buffered Output Strobe. Inputs Active on Rising

Edge. Selected to load serial data into input register and buff-

ered output stage. See Table I for details.

STB

3 (Pin 10)—Input Register and Buffered Output

Strobe Input. Active on Falling Edge. Selected to load serial

data into input register and buffered output stage. See Table I

for details.

LD

1 (Pin 5), LD2 (Pin 9)—Load DAC Register Inputs.

Active Low. Selected together to load contents of input register

into DAC register.

CLR (Pin 13)—Clear Input. Active Low. Asynchronous.

When LOW, 12-bit DAC register is forced to a zero code (0000

0000 0000) regardless of other interface inputs.