Microprocessor Interface

The AT76C001 has an 8 bit configurable microprocessor

interface comprising the following signals:

DATA <7:0>

8 bit data bus

AD– <1:0>

2 bit address bus

CS

Chip Select

DS/WR

Data Strobe or Write signal

RDWR/RD

Read/Write signal or Read signal

By setting bit 1 of the configuration interface (INTEL/

MOTO), it is possible to configure the microprocessor in-

terface to be Motorola or Intel compatible. When cho-

sen, the configuration must be locked by setting bit

LOCK_CFG of the configuration register. This must be

done first of all otherwise the circuit will not function prop-

erly.

Configuration

Motorola Mode

Intel Mode

Intel/Moto bit

Bit set to 0

Bit set to 1

Signals

DATA<7:0>

DATA<7:0>

ADD<1:0>

ADD<1:0>

CS

CS

DS

WR

RD/WR

RD

Internal Registers

The AT76C001 contains three internal registers accessi-

ble in Read and Write via the microprocessor interface,

as soon as it is configured and locked. They are:

Configuration register (CFGR)

Normalization and Rounding Register (NORR)

Filter Order Register (FILR)

Configuration Register

It is an 8 bit register mapped at address 1hex = 01bin

Bit 0 = START/STOP

Activates/deactivates filtering

Bit 1 = INTEL/MOTO

Configures microprocessor

interface to be Intel or Motorola.

Bit 2 = MSB/LSB

Indicates if 16 bit coefficients are

written with Most Significant Byte

or Least Significant Byte ahead.

Bit 3 = LOCK_CFG

Locks the microprocessor

interface configuration.

Bit 4 = SING/SEQ

Indicates the operating mode of

the 4th order cell, i.e. Single

Mode or Sequential Mode.

Bit 5 = BUFF_FULL

Indicates that the sample input

buffer contains N samples when

implementing an N-tap FIR filter.

(continued)

CL O C K

DIV

RS T _ XI

IN

OU T

DO V

X3

X4 = 0

Y0

Y1

Y 2

Y4

X0

X1

X2 = 0

X5 = 0

Y3

Timing Diagram for N-tap Filter where 4<N<9

6

AT76C001