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AT45DB161-RC Datasheet(PDF) 6 Page - ATMEL Corporation |
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AT45DB161-RC Datasheet(HTML) 6 Page - ATMEL Corporation |
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6 / 20 page  AT45DB161 6 cause the device to be in a busy state: Main Memory Page to Buffer Transfer, Main Memory Page to Buffer Compare, Buffer to Main Memory Page Program with Built-In Erase, Buffer to Main Memory Page Program without Built-In Erase, Page Erase, Block Erase, Main Memory Page Pro- gram, and Auto Page Rewrite. The result of the most recent Main Memory Page to Buffer Compare operation is indicated using bit 6 of the status register. If bit 6 is a 0, then the data in the main memory page matches the data in the buffer. If bit 6 is a 1, then at least one bit of the data in the main memory page does not match the data in the buffer. The device density is indicated using bits 5, 4, and 3 of the status register. For the AT45DB161, the three bits are 1, 0, and 1. The decimal value of these three binary bits does not equate to the device density; the three bits represent a combinational code relating to differing densities of Serial DataFlash devices, allowing a total of eight different density configurations. Read/Program Mode Summary The modes listed above can be separated into two groups — modes which make use of the flash memory array (Group A) and modes which do not make use of the flash memory array (Group B). Group A modes consist of: 1. Main Memory Page Read 2. Main Memory Page to Buffer 1 (or 2) Transfer 3. Main Memory Page to Buffer 1 (or 2) Compare 4. Buffer 1 (or 2) to Main Memory Page Program With Built-In Erase 5. Buffer 1 (or 2) to Main Memory Page Program With- out Built-In Erase 6. Page Erase 7. Block Erase 8. Main Memory Page Program 9. Auto Page Rewrite Group B modes consist of: 1. Buffer 1 (or 2) Read 2. Buffer 1 (or 2) Write 3. Status Register Read If a Group A mode is in progress (not fully completed) then another mode in Group A should not be started. However, during this time in which a Group A mode is in progress, modes in Group B can be started. This gives the Serial DataFlash the ability to virtually accommodate a continuous data stream. While data is being programmed into main memory from buffer 1, data can be loaded into buffer 2 (or vice versa). See application note AN-4 (“Using Atmel’s Serial DataFlash”) for more details. HARDWARE PAGE WRITE PROTECT: If the WP pin is held low, the first 256 pages of the main memory cannot be reprogrammed. The only way to reprogram the first 256 pages is to first drive the protect pin high and then use the program commands previously mentioned. The WP pin is internally pulled high; therefore, connection of the WP pin is not necessary if this pin and feature will not be utilized. However, it is recommended that the WP pin be driven high externally whenever possible. RESET: A low state on the reset pin (RESET) will terminate the operation in progress and reset the internal state machine to an idle state. The device will remain in the reset condition as long as a low level is present on the RESET pin. Normal operation can resume once the RESET pin is brought back to a high level. The device incorporates an internal power-on reset circuit, so there are no restrictions on the RESET pin during power-on sequences. The RESET pin is also internally pulled high; therefore, connection of the RESET pin is not necessary if this pin and feature will not be utilized. How- ever, it is recommended that the RESET pin be driven high externally whenever possible. READY/BUSY: This open drain output pin will be driven low when the device is busy in an internally self-timed oper- ation. This pin, which is normally in a high state (through an external pull-up resistor), will be pulled low during program- ming operations, compare operations, and during page-to- buffer transfers. The busy status indicates that the Flash memory array and one of the buffers cannot be accessed; read and write operations to the other buffer can still be performed. Power On/Reset State When power is first applied to the device, or when recover- ing from a reset condition, the device will default to SPI mode 3. In addition, the SO pin will be in a high impedance state, and a high to low transition on the CS pin will be required to start a valid instruction. The SPI mode will be automatically selected on every falling edge of CS by sam- pling the inactive clock state. Status Register Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RDY/BUSY COMP 1 0 1 XXX |
Similar Part No. - AT45DB161-RC |
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Similar Description - AT45DB161-RC |
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