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AT25256T2-10TI-2.7 Datasheet(PDF) 7 Page - ATMEL Corporation |
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AT25256T2-10TI-2.7 Datasheet(HTML) 7 Page - ATMEL Corporation |
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7 / 12 page  Functional Description The AT25128 is designed to interface directly with the syn- chronous serial peripheral interface (SPI) of the 6805 and 68HC11 series of microcontrollers. The AT25128 utilizes an 8 bit instruction register. The list of instructions and their operation codes are contained in Table 1. All instructions, addresses, and data are trans- ferred with the MSB first. Table 1. Instruction Set for the AT25128 Instruction Name Instruction Format Operation WREN 0000 X110 Set Write Enable Latch WRDI 0000 X100 Reset Write Enable Latch RDSR 0000 X101 Read Status Register WRSR 0000 X001 Write Status Register READ 0000 X011 Read Data from Memory Array WRITE 0000 X010 Write Data to Memory Array WRITE ENABLE (WREN): The device will power up in the write disable state when VCC is applied. All program- ming instructions must therefore be preceded by a Write Enable instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables all programming modes. The WRDI instruction is independent of the status of the WP pin. READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status register. The READY/BUSY and Write Enable status of the device can be determined by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruc- tion. Table 2a. Status Register Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WPEN X X X BP1 BP0 WEN RDY Table 2b. Read Status Register Bit Definition Bit Definition Bit 0 (RDY) Bit 0 = 0 (RDY) indicates the device is READY. Bit 0 = 1 indicates the write cycle is in progress. Bit 1 (WEN) Bit 1= 0 indicates the device is not WRITE ENABLED. Bit 1 = 1 indicates the device is WRITE ENABLED. Bit 2 (BP0) See Table 3. Bit 3 (BP1) See Table 3. Bits 4-6 are 0s when device is not in an internal write cycle. Bit 7 (WPEN) See Table 4. Bits 0-7 are 1s during an internal write cycle. WRITE STATUS REGISTER (WRSR): The WRSR in- struction allows the user to select one of four levels of pro- tection. The AT25128 is divided into four array segments. One quarter (1/4), one half (1/2), or all of the memory seg- ments can be protected. Any of the data within any se- lected segment will therefore be READ only. The block write protection levels and corresponding status register control bits are shown in Table 3. The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g. WREN, tWC, RDSR). Table 3. Block Write Protect Bits Level Status Register Bits Array Addresses Protected BP1 BP0 AT25128 0 0 0 None 1(1/4) 0 1 3000 - 3FFF 2(1/2) 1 0 2000 - 3FFF 3(All) 1 1 0000 - 3FFF The WRSR instruction also allows the user to enable or disable the write protect (WP) pin through the use of the Write Protect Enable (WPEN) bit. Hardware write protec- tion is enabled when the WP pin is low and the WPEN bit is “1.” Hardware write protection is disabled when either the WP pin is high or the WPEN bit is “0.” When the device is hardware write protected, writes to the Status Register, including the Block Protect bits and the WPEN bit, and the block-protected sections in the memory array are dis- abled. Writes are only allowed to sections of the memory which are not block-protected. NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to “0,” as long as the WP pin is held low. (continued) AT25128 7 |
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