Device Operation

READ: The AT28LV256 is accessed like a Static RAM.

When CE and OE are low and WE is high, the data stored

at the memory location determined by the address pins is

asserted on the outputs. The outputs are put in the high

impedance state when either CE or OE is high. This dual-

line control gives designers flexibility in preventing bus

contention in their system.

BYTE WRITE: A low pulse on the WE or CE input with CE

or WE low (respectively) and OE high initiates a write cy-

cle. The address is latched on the falling edge of CE or

WE, whichever occurs last. The data is latched by the first

rising edge of CE or WE. Once a byte write has been

started it will automatically time itself to completion. Once

a programming operation has been initiated and for the

ing operation.

PAGE WRITE: The p a g e wr i t e oper ation of the

AT28LV256 allows 1 to 64-bytes of data to be written into

the device during a single internal programming period. A

page write operation is initiated in the same manner as a

byte write; the first byte written can then be followed by 1

to 63 additional bytes. Each successive byte must be writ-

ten within 150

limit is exceeded the AT28LV256 will cease accepting

data and commence the internal programming operation.

All bytes during a page write operation must reside on the

same page as defined by the state of the A6 - A14 inputs.

For each WE high to low transition during the page write

operation, A6 - A14 must be the same.

The A0 to A5 inputs are used to specify which bytes within

the page are to be written. The bytes may be loaded in any

order and may be altered within the same load period.

Only bytes which are specified for writing will be written;

unnecessary cycling of other bytes within the page does

not occur.

DATA POLLING: The AT28LV256 features DATA Polling

to indicate the end of a write cycle. During a byte or page

write cycle an attempted read of the last byte written will

result in the complement of the written data to be pre-

sented on I/O7. Once the write cycle has been completed,

true data is valid on all outputs, and the next write cycle

may begin. DATA Polling may begin at anytime during the

write cycle.

TOGGLE BIT: In addition to DATA Polling the AT28LV256

provides another method for determining the end of a write

cycle. During the write operation, successive attempts to

read data from the device will result in I/O6 toggling be-

tween one and zero. Once the write has completed, I/O6

will stop toggling and valid data will be read. Reading the

toggle bit may begin at any time during the write cycle.

DATA PROTECTION: If precautions are not taken, inad-

vertent writes may occur during transitions of the host sys-

tem power supply. Atmel has incorporated both hardware

and software features that will protect the memory against

inadvertent writes.

HARDWARE PROTECTION: Hardware features protect

against inadvertent writes to the AT28LV256 in the follow-

1.8V (typical) the device will automatically time out 10 ms

(typical) before allowing a write: (b) write inhibit - holding

any one of OE low, CE high or WE high inhibits write cy-

cles; (c) noise filter - pulses of less than 15 ns (typical) on

the WE or CE inputs will not initiate a write cycle.

SOFTWARE DATA PROTECTION: A software-control-

led data protection feature has been implemented on the

AT28LV256. Software data protection (SDP) helps pre-

vent inadvertent writes from corrupting the data in the de-

vice. SDP can prevent inadvertent writes during power-up

and power-down as well as any other potential periods of

system instability.

The AT28LV256 can only be written using the software

data protection feature. A series of three write commands

to specific addresses with specific data must be presented

to the device before writing in the byte or page mode. The

same three write commands must begin each write opera-

tion. All software write commands must obey the page

mode write timing specifications. The data in the 3-byte

command sequence is not written to the device; the ad-

dress in the command sequence can be utilized just like

any other location in the device.

Any attempt to write to the device without the 3-byte se-

quence will start the internal write timers. No data will be

read operations will effectively be polling operations.

DEVICE IDENTIFICATION: A n ex t r a 64- bytes of

identification. By raising A9 to 12V

± 0.5V and using ad-

dress locations 7FC0H to 7FFFH the additional bytes may

be written to or read from in the same manner as the regu-

lar memory array.

AT28LV256

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