AT24CS128/256

7

Device Addressing

The 128K/256K EEPROM requires an 8-bit device address

word following a start condition to enable the chip for a read

or write operation (refer to Figure 1). The device address

word consists of a mandatory one, zero sequence for the

first five most significant bits as shown. This is common to

all 2-wire EEPROM devices.

The 128K/256K uses the two device address bits A1, A0 to

allow as many as four devices on the same bus. These bits

must compare to their corresponding hardwired input pins.

The A1 and A0 pins use an internal proprietary circuit that

biases them to a logic low condition if the pins are allowed

to float.

The eighth bit of the device address is the read/write opera-

tion select bit. A read operation is initiated if this bit is high

and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will

output a zero. If a compare is not made, the device will

return to a standby state.

DATA SECURITY: The AT24CS128/256 has a hardware

data protection scheme that allows the user to write protect

Write Operations

BYTE WRITE: A write operation requires two 8-bit data

word addresses following the device address word and

acknowledgment. Upon receipt of this address, the

EEPROM will again respond with a zero and then clock in

the first 8-bit data word. Following receipt of the 8-bit data

word, the EEPROM will output a zero. The addressing

device, such as a microcontroller, then must terminate the

write sequence with a stop condition. At this time the

EEPROM enters an internally-timed write cycle, t

nonvolatile memory. All inputs are disabled during this write

cycle and the EEPROM will not respond until the write is

complete (refer to Figure 2).

PAGE WRITE: The 128K/256K EEPROM is capable of 64-

byte page writes.

A page write is initiated the same way as a byte write, but

the microcontroller does not send a stop condition after the

first data word is clocked in. Instead, after the EEPROM

acknowledges receipt of the first data word, the microcon-

troller can transmit up to 63 more data words. The

EEPROM will respond with a zero after each data word

received. The microcontroller must terminate the page

write sequence with a stop condition (refer to Figure 3).

The data word address lower 6 bits are internally incre-

mented following the receipt of each data word. The higher

data word address bits are not incremented, retaining the

memory page row location. When the word address, inter-

nally generated, reaches the page boundary, the following

byte is placed at the beginning of the same page. If more

than 64 data words are transmitted to the EEPROM, the

data word address will “roll over” and previous data will be

overwritten. The address “roll over” during write is from the

last byte of the current page to the first byte of the same

page.

ACKNOWLEDGE POLLING: Once the internally-timed

write cycle has started and the EEPROM inputs are dis-

abled, acknowledge polling can be initiated. This involves

sending a start condition followed by the device address

word. The read/write bit is representative of the operation

desired. Only if the internal write cycle has completed will

the EEPROM respond with a zero, allowing the read or

write sequence to continue.

OTP Description/Operation

The OTP feature provides the user with a 2048-bit (256 x 8)

security section, which once programmed and enabled,

becomes read-only and data cannot be changed or over-

written. The OTP section is located in the upper 2K section

of the memory array in the AT24CS128/256. If not enabled,

the OTP section will function as part of the normal memory

array.

To enable the OTP section:

1.

Inputs must be connected:

2.

Initiate the programming sequence:

START 1010 1100 11xx xxxx xxxx xxxx xxxx xxxx STOP

Once enabled, previously written data cannot be changed.

The status of the OTP section can only be confirmed by ini-

tiating a programming sequence to the OTP section and

verifying by a read command. The use of the write protect

(WP) feature can be utilized with or without enabling the

OTP function.

Read Operations

Read operations are initiated the same way as write opera-

tions with the exception that the read/write select bit in the

device address word is set to one. There are three read

operations: current address read, random address read

and sequential read.

CURRENT ADDRESS READ: The internal data word

address counter maintains the last address accessed dur-

ing the last read or write operation, incremented by one.

This address stays valid between operations as long as the

chip power is maintained. The address “roll over” during

read is from the last byte of the last memory page, to the

first byte of the first page.

Once the device address with the read/write select bit set

to one is clocked in and acknowledged by the EEPROM,

the current address data word is serially clocked out. The

microcontroller does not respond with an input zero but

does generate a following stop condition (refer to Figure 4).