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AT22LV10 Datasheet(PDF) 7 Page - ATMEL Corporation |
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AT22LV10 Datasheet(HTML) 7 Page - ATMEL Corporation |
7 / 11 page AT22LV10(L) 7 Preload of Registered Outputs The registers in the AT22LV10 and AT22LV10L are pro- vided with circuitry to allow loading of each register asyn- chronously with either a high or a low. This feature will simplify testing since any state can be forced into the regis- ters to control test sequencing. A VIH level on the I/O pin will force the register high; a V IL will force it low, indepen- dent of the polarity bit (C0) setting. The preload state is entered by placing an 11.5V to 13V signal on pin 8 on DIPs, and pin 10 on SMPs. When the clock pin is pulsed high, the data on the I/O pins is placed into the ten regis- ters. Power-Up Reset The registers in the AT22LV10 and AT22LV10L are designed to reset during power up. At a point delayed slightly from VCC crossing 2.5V, all registers will be reset to the low state. The output state will depend on the polarity of the output buffer. This feature is critical for state machine initialization. How- ever, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the fol- lowing conditions are required: 1. The VCC rise must be monotonis; 2. After reset occurs, all input and feedback setup times must be met before driving the clock pin high, and 3. The clock must remain stable during t PR. Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. Erasure Characteri stics The entire fuse array of an AT22LV10 or AT22LV10L is erased after exposure to ultraviolet light at a wavelength of 2537 Å. Complete erasure is assured after a minimum of 20 minutes exposure using 12,000 µW/cm2 intensity lamps spaced one inch away from the chip. Minimum erase time for lamps at other intensity ratings can be calculated from the minimum integrated erasure dose of 15 W•sec/cm2. To prevent unintentional erasure, an opaque label is recom- mended to cover the clear window on any UV erasable PLD which will be subjected to continuous fluorescent indoor lighting or sunlight. Level forced on registered output pin during preload cycle Register state after cycle V IH High V IL Low Parameter Description Min Typ Max Units tPR Power-Up Reset Time 600 1000 ns Pin Capacitance (f = 1 MHz, T = 25°C) (1) Typ Max Units Conditions C IN 58 pF V IN = 0V C OUT 68 pF V OUT = 0V |
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Similar Description - AT22LV10 |
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