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MSC1200Y3PFBR Datasheet(PDF) 8 Page - Texas Instruments |
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MSC1200Y3PFBR Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 92 page  MSC1200 MSC1201 MSC1202 SBAS317E − APRIL 2004 − REVISED MAY 2006 www.ti.com 8 AC ELECTRICAL CHARACTERISTICS(1): DVDD = 2.7V to 5.25V MSC120x PARAMETER CONDITION MIN TYP MAX UNITS PHASE LOCK LOOP (PLL) Input Frequency Range External Crystal/Clock Frequency (fOSC) 32.768 kHz PLL LF Mode PLLDIV = 449 (default) 14.8 MHz PLL HF Mode PLLDIV = 899 (must be set by user), DVDD = 5V 29.5 MHz PLL Lock Time Within 1% 2 ms INTERNAL OSCILLATOR (IO) See Typical Characteristics IO LF Mode DVDD = 5V 14.8 MHz IO HF Mode DVDD = 5V 29.5 MHz IO Settling Time Within 1% 1 ms (1) Parameters are valid over operating temperature range, unless otherwise specified. EXTERNAL CLOCK DRIVE CLK TIMING: SEE FIGURE 1 2.7V to 3.6V 4.75V to 5.25V SYMBOL PARAMETER MIN MAX MIN MAX UNITS External Clock Mode fOSC(1) External Crystal Frequency (fOSC) 1 20 1 33 MHz 1/tOSC(1) External Clock Frequency (fOSC) 0 20 0 33 MHz fOSC(1) External Ceramic Resonator Frequency (fOSC) 1 12 1 12 MHz tHIGH High Time(2) 15 10 ns tLOW Low Time(2) 15 10 ns tR Rise Time(2) 5 5 ns tF Fall Time(2) 5 5 ns (1) tCLK = 1/fOSC = one oscillator clock period for clock divider = 1. (2) These values are characterized but not 100% production tested. t R t HIGH V IH V IH 0.8V 0.8V V IH V IH 0.8V 0.8V t LOW t OSC t F Figure 1. External Clock Drive CLK SERIAL FLASH PROGRAMMING TIMING: SEE FIGURE 2 SYMBOL PARAMETER MIN MAX UNITS tRW RST width 2 tOSC — ns tRRD RST rise to P1.0 internal pull high — 5 µs tRFD RST falling to CPU start — 18 ms tRS Input signal to RST falling setup time tOSC — ns tRH RST falling to P1.0 hold time 18 — ms NOTE: P1.0 is internally pulled−up with ~11k Ω during RST high. P1.0/PROG RST t RFD,tRH t RS t RRD t RW Figure 2. Serial Flash Programming Timing |
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