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PCM1727E2K Datasheet(PDF) 6 Page - Texas Instruments |
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PCM1727E2K Datasheet(HTML) 6 Page - Texas Instruments |
6 / 19 page PCM1727 6 SBAS077A www.ti.com DIN BCKIN LRCIN SCKO2 SCKO1 SCKO3 DATA BCK LRCK SCI XT1 18 17 19 20 7 8 9 10 ML MC MD RSTB 14 XT2 223 22 3 11 15 16 1 24 27MHz CLK OUT + 10µF Post LPF Post LPF Analog Mute Analog Mute STRB SCKO SDO PIO System Controller Rch Analog Out Lch Analog Out 12 13 MPEG Decoder Buffer 384f S AGND PGND DGND V CA +5V Analog +5V Analog V DD V CP V OUTL V OUTR ZERO CAP PCM1727 27MHz Master Clock CD-DA DSP 21 Buffer 33.8688M Karaoke DSP 6 Buffer 768/384f S TYPICAL CONNECTION DIAGRAM Figure 1 illustrates the typical connection diagram for the PCM1727 in a DVD Audio application. The 27MHz master video clock (fM) drives XT1 (pin 1) of the PCM1727. A programmable system clock is generated by the PCM1727 PLL, with SCKO2 used to drive the MPEG2 decoder system clock input, SCKO1 used to drive the CD-DA DSP system clock input, and SCKO3 used to drive Karaoke DSP system clock input. The standard audio signals (data, bit clock, and word clock) are generated in the decoder from the PCM1727 system clock, providing synchronization of audio and video signals. DUAL PLL CIRCUIT The PCM1727 has a programmable internal DUAL PLL circuit, as shown in Figure 2. The PLL is designed to accept a 27MHz master clock or crystal oscillator and generate all internal system clocks required to operate the digital filter and ∆Σ modulator, at 384f S. If an external master clock is used, XT2 must be connected to ground. In both cases, the signal amplitude on XT1 must satisfy the specification described in Figure 3. Therefore, careful C1 and C2 determi- nation is required to keep this specification satisfied when using a crystal oscillator. The PLL will directly track any variations in the master clock frequency, and jitter on the FIGURE 1. Connection Diagram for External Master Clock in a Typical MPEG2 Application. FIGURE 2. PLL Block Diagram. Oscillator XT2 XT1 MCKO 27MHz Phase Detector and Loop Filter VCO PLL1 PLL2 M Counter N Counter Counter P 24 1 4 SCKO1 33.8688MHz 21 SCKO3 768fs/384fs 6 SCKO2 384fs Internal System Clock 20 Data ROM Frequency Control Phase Detector and Loop Filter VCO N Counter M Counter |
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