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MAX192BEAP Datasheet(PDF) 10 Page - Maxim Integrated Products |
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MAX192BEAP Datasheet(HTML) 10 Page - Maxim Integrated Products |
10 / 24 page Low-Power, 8-Channel, Serial 10-Bit ADC 10 ______________________________________________________________________________________ $FF (HEX), which trigger single-ended conversions on CH7 in external clock mode without powering down between conversions. In external clock mode, the SSTRB output pulses high for one clock period before the most significant bit of the conversion result comes out of DOUT. Varying the analog input to CH7 should alter the sequence of bits from DOUT. A total of 15 clock cycles is required per conversion. All transitions of the SSTRB and DOUT outputs occur on the falling edge of SCLK. How to Start a Conversion A conversion is started on the MAX192 by clocking a control byte into DIN. Each rising edge on SCLK, with CS low, clocks a bit from DIN into the MAX192’s internal shift register. After CS falls, the first arriving logic “1” bit defines the MSB of the control byte. Until this first “start” bit arrives, any number of logic “0” bits can be clocked into DIN with no effect. Table 3 shows the control-byte format. The MAX192 is compatible with Microwire, SPI, and QSPI devices. For SPI, select the correct clock polarity and sampling edge in the SPI control registers: set CPOL = 0 and CPHA = 0. Microwire and SPI both transmit a byte and receive a byte at the same time. Using the Typical Operating Circuit, the simplest soft- ware interface requires only three 8-bit transfers to per- form a conversion (one 8-bit transfer to configure the ADC, and two more 8-bit transfers to clock out the 12-bit conversion result). Example: Simple Software Interface Make sure the CPU’s serial interface runs in master mode so the CPU generates the serial clock. Choose a clock frequency from 100kHz to 2MHz. 1) Set up the control byte for external clock mode, call it TB1. TB1 should be of the format: 1XXXXX11 binary, where the Xs denote the par- ticular channel and conversion-mode selected. 2) Use a general-purpose I/O line on the CPU to pull CS on the MAX192 low. 3) Transmit TB1 and simultaneously receive a byte and call it RB1. Ignore RB1. 4) Transmit a byte of all zeros ($00 HEX) and simultaneously receive byte RB2. 5) Transmit a byte of all zeros ($00 HEX) and simultaneously receive byte RB3. 6) Pull CS on the MAX192 high. Figure 6 shows the timing for this sequence. Bytes RB2 and RB3 will contain the result of the conversion padded with one leading zero, two sub-LSB bits, and three trailing zeros. The total conversion time is a func- tion of the serial clock frequency and the amount of dead time between 8-bit transfers. Make sure that the total conversion time does not exceed 120µs, to avoid excessive T/H droop. Digital Output In unipolar input mode, the output is straight binary (Figure 15). For bipolar inputs in differential mode, the output is twos-complement (Figure 16). Data is clocked out at the falling edge of SCLK in MSB-first format. Internal and External Clock Modes The MAX192 may use either an external serial clock or the internal clock to perform the successive-approxima- tion conversion. In both clock modes, the external clock shifts data in and out of the MAX192. The T/H acquires the input signal as the last three bits of the control byte are clocked into DIN. Bits PD1 and PD0 of the control byte program the clock mode. Figures 7 through 10 show the timing characteristics common to both modes. REFERENCE ZERO SCALE FULL SCALE Internal Reference 0V +4.096V External Reference 0V VREF at REFADJ at VREF 0V VREFADJ (1.678) Table 4a. Unipolar Full Scale and Zero Scale Table 4b. Differential Bipolar Full Scale, Zero Scale, and Negative Full Scale REFERENCE NEGATIVE FULL SCALE FULL SCALE Internal Reference -4.096V / 2 +4.096V / 2 External Reference -1/2VREFADJ (1.678) +1/2VREF at REFADJ 0.at VREF -1/2VREF +1/2VREFADJ (1.678) ZERO SCALE 0V 0V 0V |
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