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EP2SGX90E Datasheet(PDF) 7 Page - Altera Corporation |
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EP2SGX90E Datasheet(HTML) 7 Page - Altera Corporation |
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7 / 316 page  Altera Corporation 1–5 October 2007 Stratix II GX Device Handbook, Volume 1 Introduction Referenced Document This chapter references the following document: ■ Stratix II GX Architecture chapter in volume 1 of the Stratix II GX Device Handbook Document Revision History Table 1–4 shows the revision history for this chapter. Table 1–3. Stratix II GX FineLine BGA Package Sizes Dimension 780 Pins 1,152 Pins 1,508 Pins Pitch (mm) 1.00 1.00 1.00 Area (mm2) 841 1,225 1,600 Length width (mm × mm) 29 × 29 35 × 35 40 × 40 Table 1–4. Document Revision History Date and Document Version Changes Made Summary of Changes October 2007, v1.6 Updated “Features” section. Minor text edits. August 2007, v1.5 Added “Referenced Documents” section. Minor text edits. February 2007, v1.4 ● Changed 622 Mbps to 600 Mbps on page 1-2 and Table 1–1. ● Deleted “DC coupling” from the Transceiver Block Features list. ● Changed 4 to 6 in the PLLs row (columns 3 and 4) of Table 1–1. Added the “Document Revision History” section to this chapter. Added support information for the Stratix II GX device. June 2006, v1.3 ● Updated Table 1–2. April 2006, v1.2 ● Updated Table 1–1. ● Updated Table 1–2. Updated numbers for receiver channels and user I/O pin counts in Table 1–2. February 2006, v1.1 ● Updated Table 1–1. October 2005 v1.0 Added chapter to the Stratix II GX Device Handbook. |
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