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EP2SGX60D Datasheet(PDF) 5 Page - Altera Corporation |
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EP2SGX60D Datasheet(HTML) 5 Page - Altera Corporation |
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5 / 316 page  Altera Corporation 1–3 October 2007 Stratix II GX Device Handbook, Volume 1 Introduction ● 8B/10B encoder and decoder perform 8-bit to 10-bit encoding and 10-bit to 8-bit decoding ● Phase compensation FIFO buffer performs clock domain translation between the transceiver block and the logic array ● Receiver FIFO resynchronizes the received data with the local reference clock ● Channel aligner compliant with XAUI f Certain transceiver blocks can be bypassed. Refer to the Stratix II GX Architecture chapter in volume 1 of the Stratix II GX Device Handbook for more details. Table 1–1 lists the Stratix II GX device features. Table 1–1. Stratix II GX Device Features (Part 1 of 2) Feature EP2SGX30C/D EP2SGX60C/D/E EP2SGX90E/F EP2SGX130/G CD C D E E F G ALMs 13,552 24,176 36,384 53,016 Equivalent LEs 33,880 60,440 90,960 132,540 Transceiver channels 48 4 8 12 12 16 20 Transceiver data rate 600 Mbps to 6.375 Gbps 600 Mbps to 6.375 Gbps 600 Mbps to 6.375 Gbps 600 Mbps to 6.375 Gbps Source-synchronous receive channels (1) 31 31 31 42 47 59 73 Source-synchronous transmit channels 29 29 29 42 45 59 71 M512 RAM blocks (32 × 18 bits) 202 329 488 699 M4K RAM blocks (128 × 36 bits) 144 255 408 609 M-RAM blocks (4K × 144 bits) 12 4 6 Total RAM bits 1,369,728 2,544,192 4,520,448 6,747,840 Embedded multipliers (18 × 18) 64 144 192 252 DSP blocks 16 36 48 63 PLLs 4 4 4 8 8 8 Maximum user I/O pins 361 364 364 534 558 650 734 |
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