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AY0438I Datasheet(PDF) 2 Page - Microchip Technology |
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AY0438I Datasheet(HTML) 2 Page - Microchip Technology |
2 / 11 page AY0438 DS70010I-page 2 © 1995 Microchip Technology Inc. FIGURE 1: PIN DESCRIPTIONS Pin # (PDIP Only) Name Direction Description 1VDD - Supply voltage 2 Load Input Latch data from registers 3-29, 32, 33, 37-39 Seg 1-32 Output Direct drive outputs 30 BP Output Backplane drive output 31 LCD Φ Input Backplane drive input 34 Data In Input Data input to shift register 35 Data Out Output Data output from shift register 36 VSS Ground Ground 40 Clock Input System clock input FIGURE 2: BLOCK DIAGRAM 32 Latches Clock Data in Load LCD Φ Data out 32 Outputs Backplane output 32 Segment Drivers LCD AC Generator 32-bit Static Shift Register FIGURE 3: BACKPLANE AND SEGMENT OUTPUT SEG On Backplane SEG Off FIGURE 4: TIMING DIAGRAM START CLOCK Data in Data out Load 1/f tDS tDH tPD 32 1 tPW 31 SEG 32 SEG 2 SEG 1 1.0 OPERATION: 1.1 Data In and Clock The shift register shifts and outputs on the falling edge of the clock. Every clock falling edge does a logical left shift. As an example, if 32 clock pulses are supplied as in Figure 4, then the data input at the first clock will out- put at SEG 32, and the last data input (# 32) will output at SEG 1 when a LOAD signal is enabled (Figure 2). It is recommended that a complete 32 bit transfer be done every time the outputs are updated. A logic 1 at the Data In causes the corresponding segment to be enabled or visible, i.e. the output at Segment Output is 180 ° out-of-phase with the Backplane output (Figure 3). 1.2 Load A logic 1 at the Load input (Figure 2) causes the paral- lel load of the data in the shift register into the latches that control the segment drivers. If the Load signal is tied high, then the latches become transparent and the segment drivers are always connected to the shift reg- isters. |
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