AOZ5066

Rev. 1.0 August 2013

www.aosmd.com

Page 3 of 16

Pin Description

Functional Block Diagram

Pin Number

Pin Name

Pin Function

1

SMOD

Skip Mode input. When the pin is held active low, Diode Emulation or Skip Mode is enabled for

the LS FET.

2

VCIN

Control supply input. Nominal 5V. Can be derived from the gate drive supply VDRV with an RC

filter for noise bypass.

3

VDRV

Gate drive supply input. Nominal 5V.

4

BOOT

Gate drive supply for the HS FET. Nominal 5V. The bootstrap diode is internal to the module.

Connect a 0.1

F or higher ceramic capacitor between VSWH node at pin 7.

5, 37

CGND

Control or analog ground for return of control signals and bypass capacitors.

Attached to exposed pad in the driver section.

6

GH

Gate of the HS FET. Used for module testing during production. No user connections.

7

VSWH

Switching or the phase node for bootstrap capacitor connection.

8 to 14

VIN

Power input to the switching MOSFETs. Attached to the HS FET drain tab.

15

VSWH

Switching or the phase node pin. Not for power connections.

16 to 28

PGND

Power ground. Internally connected to control GND of pin 37.

29 to 35

VSWH

Switching or phase node connected to source of high side MOSFET and drain of the low side

MOSFET. Electrically attached to the LS FET drain tab.

36

GL

Gate of the LS FET. Used for module testing during production. No user connections.

38

THDN

Open drain output of the thermal shutdown circuit. Active low.

39

DISB#

Disable pin for the controller. Both gates are held active low when DISB# is grounded.

40

PWM

Pulse Width Modulated Tri State input from external controller.

VDRV

BOOT

VIN

VSWH

PGND

VCIN

PWM

DISB#

SMOD

THDN

VDRV

CGND

Temp

SHDN

VCIN

UVLO

Complementary

Control Logic

Shoot

Through

Control