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ADSP-21060LCW-160 Datasheet(PDF) 1 Page - Analog Devices |
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ADSP-21060LCW-160 Datasheet(HTML) 1 Page - Analog Devices |
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1 / 48 page  REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a ADSP-21060 Industrial SHARC® DSP Microcomputer Family ADSP-21060C/ADSP-21060LC Efficient Program Sequencing with Zero-Overhead Looping: Single-Cycle Loop Setup IEEE JTAG Standard 1149.1 Test Access Port and On-Chip Emulation 240-Lead Thermally Enhanced CQFP Package 32-Bit Single-Precision and 40-Bit Extended-Precision IEEE Floating-Point Data Formats or 32-Bit Fixed- Point Data Format Parallel Computations Single-Cycle Multiply and ALU Operations in Parallel with Dual Memory Read/Writes and Instruction Fetch Multiply with Add and Subtract for Accelerated FFT Butterfly Computation 4 Mbit On-Chip SRAM Dual-Ported for Independent Access by Core Processor and DMA Off-Chip Memory Interfacing 4 Gigawords Addressable Programmable Wait State Generation, Page-Mode DRAM Support SHARC is a registered trademark of Analog Devices, Inc. SERIAL PORTS (2) LINK PORTS (6) 4 6 6 36 IOP REGISTERS (MEMORY MAPPED) CONTROL, STATUS & DATA BUFFERS I/O PROCESSOR TIMER INSTRUCTION CACHE 32 x 48-BIT ADDR DATA DATA DATA ADDR ADDR DATA ADDR TWO INDEPENDENT DUAL-PORTED BLOCKS PROCESSOR PORT I/O PORT JTAG TEST & EMULATION 7 HOST PORT ADDR BUS MUX IOA 17 IOD 48 MULTIPROCESSOR INTERFACE DUAL-PORTED SRAM EXTERNAL PORT DATA BUS MUX 48 32 24 PM ADDRESS BUS DM ADDRESS BUS PM DATA BUS DM DATA BUS BUS CONNECT (PX) DATA REGISTER FILE 16 x 40-BIT BARREL SHIFTER ALU MULTIPLIER DAG1 8 x 4 x 32 32 48 40/32 CORE PROCESSOR DMA CONTROLLER PROGRAM SEQUENCER DAG2 8 x 4 x 24 Figure 1. Block Diagram SUMMARY High Performance Signal Processor for Communica- tions, Graphics, and Imaging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch, Instruction Fetch, and Nonintrusive I/O 32-Bit IEEE Floating-Point Computation Units— Multiplier, ALU, and Shifter Dual-Ported On-Chip SRAM and Integrated I/O Peripherals—A Complete System-On-A-Chip Integrated Multiprocessing Features Industrial Temperature Grade Hermetic Ceramic QFP Package KEY FEATURES 40 MIPS, 25 ns Instruction Rate, Single-Cycle Instruction Execution 120 MFLOPS Peak, 80 MFLOPS Sustained Performance Dual Data Address Generators with Modulo and Bit- Reverse Addressing One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 |
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