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ADSP-21060LCW-133 Datasheet(PDF) 11 Page - Analog Devices |
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ADSP-21060LCW-133 Datasheet(HTML) 11 Page - Analog Devices |
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11 / 48 page  ADSP-21060C/ADSP-21060LC –11– REV. B TARGET BOARD CONNECTOR FOR EZ-ICE PROBE The ADSP-2106x EZ-ICE Emulator uses the IEEE 1149.1 JTAG test access port of the ADSP-2106x to monitor and control the target board processor during emulation. The EZ-ICE probe requires the ADSP-2106x’s CLKIN, TMS, TCK, TRST, TDI, TDO, EMU, and GND signals be made accessible on the target system via a 14-pin connector (a 2 row × 7 pin strip header) such as that shown in Figure 5. The EZ-ICE probe plugs directly onto this connector for chip-on-board emulation. You must add this connector to your target board design if you intend to use the ADSP-2106x EZ-ICE. The total trace length between the EZ- ICE connector and the furthest device sharing the EZ-ICE JTAG pins should be limited to 15 inches maximum for guaran- teed operation. This length restriction must include EZ-ICE JTAG signals that are routed to one or more ADSP-2106x devices, or a combination of ADSP-2106x devices and other JTAG devices on the chain. TOP VIEW 13 14 11 12 910 9 78 56 34 12 EMU CLKIN (OPTIONAL) TMS TCK TRST TDI TDO GND KEY (NO PIN) BTMS BTCK BTRST BTDI GND Figure 5. Target Board Connector for ADSP-2106x EZ-ICE Emulator (Jumpers in Place) ADSP-2106x #1 JTAG DEVICE (OPTIONAL) ADSP-2106x n TDI EZ-ICE JTAG CONNECTOR OTHER JTAG CONTROLLER OPTIONAL EMU TMS TCK TDO CLKIN TRST TDI TDO TDI TDO TDO TDI Figure 6. JTAG Scan Path Connections for Multiple ADSP-2106x Systems The 14-pin, 2-row pin strip header is keyed at the Pin 3 location — Pin 3 must be removed from the header. The pins must be 0.025 inch square and at least 0.20 inch in length. Pin spacing should be 0.1 × 0.1 inches. Pin strip headers are available from vendors such as 3M, McKenzie and Samtec. The BTMS, BTCK, BTRST and BTDI signals are provided so the test access port can also be used for board-level testing. When the connector is not being used for emulation, place jumpers between the Bxxx pins and the xxx pins. If the test access port will not be used for board testing, tie BTRST to GND and tie or pull BTCK up to VDD. The TRST pin must be asserted after power-up (through BTRST on the connector) or held low for proper operation of the ADSP-2106x. None of the Bxxx pins (Pins 5, 7, 9, 11) are connected on the EZ-ICE probe. The JTAG signals are terminated on the EZ-ICE probe as follows: Signal Termination TMS Driven through 22 Ω Resistor (16 mA Driver) TCK Driven at 10 MHz through 22 Ω Resistor (16 mA Driver) TRST* Active Low Driven through 22 Ω Resistor (16 mA Driver) (Pulled Up by On-Chip 20 k Ω Resistor) TDI Driven by 22 Ω Resistor (16 mA Driver) TDO One TTL Load, Split Termination (160/220) CLKIN One TTL Load, Split Termination (160/220) EMU Active Low 4.7 k Ω Pull-Up Resistor, One TTL Load (Open-Drain Output from the DSP) *TRST is driven low until the EZ-ICE probe is turned on by the emulator at software start-up. After software start-up, TRST is driven high. Figure 6 shows JTAG scan path connections for systems that contain multiple ADSP-2106x processors. |
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