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ADM706TAR-REEL Datasheet(PDF) 6 Page - Analog Devices |
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ADM706TAR-REEL Datasheet(HTML) 6 Page - Analog Devices |
6 / 16 page ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T Rev. C | Page 6 of 16 TOP VIEW (Not to Scale) PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS RESET ADM706P 1 2 3 4 5 8 7 6 PFO MR WDI WDO VCC GND PFI RESET 1 TOP VIEW (Not to Scale) 2 3 4 5 8 7 6 PFO MR WDI VCC GND PFI WDO ADM706R/ ADM706S/ ADM706T Figure 3. ADM706P Figure 4. ADM706R/ADM706S/ADM706T Table 3. Pin Function Descriptions ADM706P/ADM706R/ADM706S/ADM706T Pin No. Mnemonic Description 1 MR Manual Reset Input. When taken below 0.6 V, a RESET/RESET is generated. MR can be driven from TTL, CMOS logic, or from a manual reset switch because it is internally debounced. An internal 70 μA pull-up current holds the input high when floating. 2 VCC Power Supply Input. 3 GND Ground. Ground reference for all signals (0 V). 4 PFI Power-Fail Input. PFI is the noninverting input to the power-fail comparator. When PFI is less than 1.25 V, PFO goes low. If unused, PFI should be connected to GND. 5 PFO Power-Fail Output. PFO is the output from the power-fail comparator. It goes low when PFI is less than 1.25 V. 6 WDI Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout period, the watchdog output, WDO, goes low. The timer resets with each transition at the WDI input. Either a high-to-low or a low-to-high transition clears the counter. The internal timer is also cleared whenever reset is asserted. 7 (ADM706R/ADM706S/ ADM706T Only) RESET Logic Output. RESET goes low for 200 ms when triggered. It is triggered either by VCC being below the reset threshold or by a low signal on the MR input. RESET remains low whenever VCC is below the reset threshold. It remains low for 200 ms after VCC goes above the reset threshold or MR goes from low to high. A watchdog timeout does not trigger RESET unless WDO is connected to MR. 7 (ADM706P Only) RESET Logic Output. RESET is an active high output suitable for systems that use active high reset logic. It is the inverse of RESET. 8 WDO Watchdog Output. WDO goes low if the internal watchdog timer times out as a result of inactivity on the WDI input. It remains low until the watchdog timer is cleared. WDO also goes low during low line conditions. Whenever VCC is below the reset threshold, WDO remains low. As soon as VCC goes above the reset threshold, WDO goes high immediately. |
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