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ISL6208IBZ Datasheet(PDF) 8 Page - Intersil Corporation |
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ISL6208IBZ Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 13 page ISL6208, ISL6208B 8 FN9115.6 January 31, 2012 Diode Emulation Diode emulation allows for higher converter efficiency under light load situations. With diode emulation active, the ISL6208 will detect the zero current crossing of the output inductor and turn off LGATE. This ensures that discontinuous conduction mode (DCM) is achieved. Diode emulation is asynchronous to the PWM signal. Therefore, the ISL6208 will respond to the FCCM input immediately after it changes state. Refer to“Typical Performance Waveforms” on page 7. NOTE: Intersil does not recommend Diode Emulation use with rDS(ON) current sensing topologies. The turn-OFF of the low side MOSFET can cause gross current measurement inaccuracies. Three-State PWM Input A unique feature of the ISL6208 and other Intersil drivers is the addition of a shutdown window to the PWM input. If the PWM signal enters and remains within the shutdown window for a set holdoff time, the output drivers are disabled and both MOSFET gates are pulled and held low. The shutdown state is removed when the PWM signal moves outside the shutdown window. Otherwise, the PWM rising and falling thresholds outlined in the “Electrical Specifications” table on page 3 determine when the lower and upper gates are enabled. Adaptive Shoot-Through Protection Both drivers incorporate adaptive shoot-through protection to prevent upper and lower MOSFETs from conducting simultaneously and shorting the input supply. This is accomplished by ensuring the falling gate has turned off one MOSFET before the other is allowed to turn on. During turn-off of the lower MOSFET, the LGATE voltage is monitored until it reaches a 1V threshold, at which time the UGATE is released to rise. Adaptive shoot-through circuitry monitors the upper MOSFET gate-to-source voltage during UGATE turn-off. Once the upper MOSFET gate-to-source voltage has dropped below a threshold of 1V, the LGATE is allowed to rise. Internal Bootstrap Diode This driver features an internal bootstrap Schottky diode. Simply adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit. The bootstrap capacitor must have a maximum voltage rating above the maximum battery voltage plus 5V. The bootstrap capacitor can be chosen from Equation 1: where QGATE is the amount of gate charge required to fully charge the gate of the upper MOSFET. The ΔVBOOT term is defined as the allowable droop in the rail of the upper drive. As an example, suppose an upper MOSFET has a gate charge, QGATE, of 25nC at 5V and also assume the droop in the drive voltage over a PWM cycle is 200mV. One will find that a bootstrap capacitance of at least 0.125µF is required. The next larger standard value capacitance is 0.15µF. A good quality ceramic capacitor is recommended. Power Dissipation Package power dissipation is mainly a function of the switching frequency and total gate charge of the selected MOSFETs. Calculating the power dissipation in the driver for a desired application is critical to ensuring safe operation. Exceeding the maximum allowable power dissipation level will push the IC beyond the maximum recommended operating junction temperature of +125°C. The maximum allowable IC power dissipation for the SO-8 package is approximately 800mW. When designing the driver into an application, it is recommended that the following calculation be performed to ensure safe operation at the desired frequency for the selected MOSFETs. The power dissipated by the driver is approximated as shown in Equation 2: where fsw is the switching frequency of the PWM signal. VU and VL represent the upper and lower gate rail voltage. QU and QL is the upper and lower gate charge determined by MOSFET selection and any external capacitance added to the gate pins. The lVCC VCC product is the quiescent power of the driver and is typically negligible. CBOOT QGATE ΔV BOOT --------------------- ≥ (EQ. 1) FIGURE 8. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE VOLTAGE 20nC ΔVBOOT_CAP (V) 2.0 1.6 1.4 1.0 0.8 0.6 0.4 0.2 0.0 0.3 0.0 0.1 0.2 0.4 0.5 0.6 0.9 0.7 0.8 1.0 QGATE = 100nC 1.2 1.8 Pfsw 1.5VUQU VLQL + () I VCCVCC + = (EQ. 2) FIGURE 9. POWER DISSIPATION vs FREQUENCY FREQUENCY (kHz) 0 100 200 300 400 500 600 700 800 900 1000 0 200 400 600 800 1000 1200 1400 1600 1800 2000 QU = 50nC QL = 50nC QU = 50nC QL = 100nC QU =100nC QL = 200nC QU = 20nC QL =50nC |
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