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AD5254BRUZ10 Datasheet(PDF) 4 Page - Analog Devices |
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AD5254BRUZ10 Datasheet(HTML) 4 Page - Analog Devices |
4 / 32 page AD5253/AD5254 Data Sheet Rev. C | Page 4 of 32 Parameter Symbol Conditions Min Typ1 Max Unit DIGITAL INPUTS AND OUTPUTS Input Logic High V IH V DD = 5 V, VSS = 0 V 2.4 V V DD/VSS = +2.7 V/0 V or VDD/VSS = ±2.5 V 2.1 V Input Logic Low V IL V DD = 5 V, VSS = 0 V 0.8 V V DD/VSS = +2.7 V/0 V or VDD/VSS = ±2.5 V 0.6 V Output Logic High (SDA) V OH R PULL-UP = 2.2 kΩ to VDD = 5 V, VSS = 0 V 4.9 V Output Logic Low (SDA) V OL R PULL-UP = 2.2 kΩ to VDD = 5 V, VSS = 0 V 0.4 V WP Leakage Current I WP WP = VDD 8 µA A0 Leakage Current I A0 A0 = GND 3 µA Input Leakage Current (Other than WP and A0) I I V IN = 0 V or VDD ±1 µA Input Capacitance5 C I 5 pF POWER SUPPLIES Single-Supply Power Range V DD V SS = 0 V 2.7 5.5 V Dual-Supply Power Range V DD/VSS ±2.25 ±2.75 V Positive Supply Current I DD V IH = VDD or VIL = GND 5 15 µA Negative Supply Current I SS V IH = VDD or VIL = GND, VDD = 2.5 V, V SS = –2.5 V –5 –15 µA EEMEM Data Storing Mode Current I DD_STORE V IH = VDD or VIL = GND 35 mA EEMEM Data Restoring Mode Current6 I DD_RESTORE V IH = VDD or VIL = GND 2.5 mA Power Dissipation7 P DISS V IH = VDD = 5 V or VIL = GND 0.075 mW Power Supply Sensitivity PSS ΔV DD = 5 V ± 10% −0.025 +0.010 +0.025 %/% ΔV DD = 3 V ± 10% –0.04 +0.02 +0.04 %/% DYNAMIC CHARACTERISTICS5, 8 Bandwidth –3 dB BW R AB = 1 kΩ 4 MHz Total Harmonic Distortion THD V A =1 V rms, VB = 0 V, f = 1 kHz 0.05 % V W Settling Time t S V A = VDD, VB = 0 V 0.2 µs Resistor Noise Voltage e N_WB R WB = 500 Ω, f = 1 kHz (thermal noise only) 3 nV/√Hz Digital Crosstalk C T V A = VDD, VB = 0 V, measure VW with adjacent RDAC making full-scale change –80 dB Analog Coupling C AT Signal input at A0 and measure the output at W1, f = 1 kHz –72 dB 1 Typical values represent average readings at 25°C and V DD = 5 V. 2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL is the relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5254 1 kΩ version at VDD = 2.7 V, IW = VDD/R for both VDD = 3 V and VDD = 5 V. 3 INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output digital-to-analog converter. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 4 Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other. 5 Guaranteed by design and not subject to production test. 6 Command 0 NOP should be activated after Command 1 to minimize I DD_RESTORE current consumption. 7 P DISS is calculated from IDD × VDD = 5 V. 8 All dynamic characteristics use V DD = 5 V. |
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