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MPC8347ECZQALDB Datasheet(PDF) 2 Page - Freescale Semiconductor, Inc |
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MPC8347ECZQALDB Datasheet(HTML) 2 Page - Freescale Semiconductor, Inc |
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2 / 99 page  MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 2 Freescale Semiconductor Overview NOTE The information in this document is accurate for revision 3.x silicon and later (in other words, for orderable part numbers ending in A or B). For information on revision 1.1 silicon and earlier versions, see the MPC8347E PowerQUICC II Pro Integrated Host Processor Hardware Specifications. See Section 22.1, “Part Numbers Fully Addressed by This Document,” for silicon revision level determination. 1 Overview This section provides a high-level overview of the device features. Figure 1 shows the major functional units within the MPC8347EA. Figure 1. MPC8347EA Block Diagram Major features of the device are as follows: • Embedded PowerPC e300 processor core; operates at up to 667 MHz — High-performance, superscalar processor core — Floating-point, integer, load/store, system register, and branch processing units — 32-Kbyte instruction cache, 32-Kbyte data cache — Lockable portion of L1 cache — Dynamic power management — Software-compatible with the other Freescale processor families that implement Power Architecture technology • Double data rate, DDR1/DDR2 SDRAM memory controller — Programmable timing supporting DDR1 and DDR2 SDRAM — 32- or 64-bit data interface, up to 400 MHz data rate for TBGA, 266 MHz for PBGA DUART Dual I2C Timers GPIO Security Interrupt Controller Dual Role High-Speed Local Bus DDR SDRAM Controller Host 32KB D-Cache e300 Core 32KB I-Cache USB 2.0 10/100/1000 SEQ PCI DMA Ethernet 10/100/1000 Ethernet |
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