SW

VBST

EN

VO

VFB

GND

PGND

VO

4

6

9

10

11

1

2

7

12

VIN1

SS

VIN

5

VREG

EN

Logic

UV

OV

Protection

Logic

Ref

SS

UV

OV

UVLO

UVLO

Softstart

SS

REF

TSD

Ref

VREG5

5

PG

1 F

m

13

8

VCC

Ceramic

Capacitor

3

SGND

SGND

PGND

VIN2

+20%

-10%

Ref

VREG5

VREG5

Control logic

1 shot

XCON

-35%

OCP

SW

PGND

ZC

SW

PGND

14

TPS54426

SLVSAD6C

– AUGUST 2010 – REVISED JULY 2011

www.ti.com

FUNCTIONAL BLOCK DIAGRAM

A.

The block diagram shown is for the PWP 14 pin package. The QFN 16 pin package block diagram is identical except

for the pin out.

6

Copyright

© 2010–2011, Texas Instruments Incorporated

Product Folder Link(s) :TPS54426