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ADS5522IPAP Datasheet(PDF) 8 Page - Texas Instruments |
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ADS5522IPAP Datasheet(HTML) 8 Page - Texas Instruments |
8 / 32 page www.ti.com A3 ADDRESS SDATA MSB DATA A2 A1 A0 D11 D10 D9 D0 16 x M MSB LSB LSB MSB SCLK SEN SDATA tSLOADS tSLOADH tSCLK tWSCLK tWSCLK tsu(D) th(D) ADS5522 SBAS320C – MAY 2004 – REVISED FEBRUARY 2007 SERIAL PROGRAMMING INTERFACE CHARACTERISTICS (continued) Figure 3. DATA Communication is 2-Byte, MSB First Figure 4. Serial Programming Interface Timing Diagram Table 1. Serial Programming Interface Timing Characteristics SYMBOL PARAMETER MIN(1) TYP(1) MAX(1) UNIT tSCLK SCLK period 50 ns tWSCLK SCLK duty cycle 25% 50% 75% tSLOADS SEN to SCLK setup time 8 ns tSLOADH SCLK to SEN hold time 6 ns tDS Data setup time 8 ns tDH Data hold time 6 ns (1) Typ, min, and max values are characterized, but not production tested. Table 2. Serial Register Table(1) A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DESCRIPTION TP<1 TP<0 Test Mode > > 1 1 1 0 0 0 0 0 0 0 0 0 0 0 X 0 Normal mode of operation 1 1 1 0 0 0 1 0 0 0 0 0 0 0 X 0 All outputs forced to 0(2) 1 1 1 0 0 1 0 0 0 0 0 0 0 0 X 0 All outputs forced to 1(2) 1 1 1 0 0 1 1 0 0 0 0 0 0 0 X 0 Each output bit toggles between 0 and 1. (2)(3) PDN Power Down 1 1 1 1 0 0 0 0 0 0 0 0 0 0 X 0 Normal mode of operation 1 1 1 1 1 0 0 0 0 0 0 0 0 0 X 0 Device is put in power-down (low-current) mode. (1) The register contents default to the appropriate setting for normal operation up on RESET. (2) The patterns given are applicable to the straight offset binary output format. If two's complement output format is selected, the test mode outputs will be the binary two's complement equivalent of these patterns as described in the Output Information section. (3) While each bit toggles between 1 and 0 in this mode, there is no assured phase relationship between the data bits D0 through D11. For example, when D0 is a 1, D1 in not assured to be a 0, and vice versa. 8 Submit Documentation Feedback |
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