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LPC1825JET100 Datasheet(PDF) 2 Page - NXP Semiconductors |
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LPC1825JET100 Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 147 page LPC185X_3X_2X_1X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Preliminary data sheet Rev. 4 — 31 October 2012 2 of 147 NXP Semiconductors LPC185x/3x/2x/1x 32-bit ARM Cortex-M3 microcontroller Ultra-low power RTC crystal oscillator. Three PLLs allow CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. The second PLL can be used with the High-speed USB, the third PLL can be used as audio PLL. Clock output. Configurable digital peripherals: State Configurable Timer (SCT) subsystem on AHB. Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and outputs to event driven peripherals like timers, SCT, and ADC0/1. Serial interfaces: Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to 52 MB per second. 10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time stamping (IEEE 1588-2008 v2). One High-speed USB 2.0 Host/Device/OTG interface with DMA support and on-chip high-speed PHY (USB0). One High-speed USB 2.0 Host/Device interface with DMA support, on-chip full-speed PHY and ULPI interface to an external high-speed PHY (USB1). USB interface electrical test software included in ROM USB stack. Four 550 UARTs with DMA support: one UART with full modem interface; one UART with IrDA interface; three USARTs support UART synchronous mode and a smart card interface conforming to ISO7816 specification. Up to two C_CAN 2.0B controllers with one channel each. Use of C_CAN controller excludes operation of all other peripherals connected to the same bus bridge See Figure 1 and Ref. 1. Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA support. One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O pins conforming to the full I2C-bus specification. Supports data rates of up to 1Mbit/s. One standard I2C-bus interface with monitor mode and standard I/O pins. Two I2S interfaces with DMA support, each with one input and one output. Digital peripherals: External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash, and SDRAM devices. LCD controller with DMA support and a programmable display resolution of up to 1024H 768V. Supports monochrome and color STN panels and TFT color panels; supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct pixel mapping. SD/MMC card interface. Eight-channel General-Purpose DMA controller can access all memories on the AHB and all DMA-capable AHB slaves. Up to 164 General-Purpose Input/Output (GPIO) pins with configurable pull-up/pull-down resistors. GPIO registers are located on the AHB for fast access. GPIO ports have DMA support. |
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