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PDTC114EU Datasheet(PDF) 3 Page - NXP Semiconductors |
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PDTC114EU Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 17 page PDTC114E_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 12 — 21 December 2011 3 of 17 NXP Semiconductors PDTC114E series NPN resistor-equipped transistors; R1 = 10 k , R2 = 10 k 5. Limiting values [1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint. [2] Reflow soldering is the only recommended soldering method. [3] Device mounted on an FR4 PCB with 70 m copper strip line, standard footprint. Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VCBO collector-base voltage open emitter - 50 V VCEO collector-emitter voltage open base - 50 V VEBO emitter-base voltage open collector - 10 V VI input voltage positive - +40 V negative - 10 V IO output current - 100 mA ICM peak collector current single pulse; tp 1ms - 100 mA Ptot total power dissipation Tamb 25 C PDTC114EE (SOT416) [1][2] -150 mW PDTC114EM (SOT883) [2][3] -250 mW PDTC114ET (SOT23) [1] -250 mW PDTC114EU (SOT323) [1] -200 mW Tj junction temperature - 150 C Tamb ambient temperature 65 +150 C Tstg storage temperature 65 +150 C |
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