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BZA856AVL Datasheet(PDF) 8 Page - NXP Semiconductors |
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BZA856AVL Datasheet(HTML) 8 Page - NXP Semiconductors |
8 / 11 page 2003 Oct 20 8 NXP Semiconductors Product data sheet Quadruple low capacitance ESD suppressor BZA800AVL series Device placement and printed-circuit board layout Circuit board layout is of extreme importance in the suppression of transients. The clamping voltage of the BZA800AVL is determined by the peak transient current and the rate of rise of that current (di/dt). Since parasitic inductances can further add to the clamping voltage (V = L di/dt) the series conductor lengths on the printed-circuit board should be kept to a minimum. This includes the lead length of the suppression element. In addition to minimizing conductor length the following printed-circuit board layout guidelines are recommended: 1. Place the suppression element close to the input terminals or connectors 2. Keep parallel signal paths to a minimum 3. Avoid running protection conductors in parallel with unprotected conductors 4. Minimize all printed-circuit board loop areas including power and ground loops 5. Minimize the length of the transient return path to ground 6. Avoid using shared transient return paths to a common ground point. |
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