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ADSP-21363KBC-1AA Datasheet(PDF) 9 Page - Analog Devices

Part # ADSP-21363KBC-1AA
Description  SHARC Processors
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADSP-21363KBC-1AA Datasheet(HTML) 9 Page - Analog Devices

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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Rev. G
|
Page 9 of 56
|
March 2011
Target Board JTAG Emulator Connector
Analog Devices’ DSP Tools product line of JTAG emulators
uses the IEEE 1149.1 JTAG test access port of the processor to
monitor and control the target board processor during emula-
tion. Analog Devices’ DSP Tools product line of JTAG
emulators provides emulation at full processor speed, allowing
inspection and modification of memory, registers, and proces-
sor stacks. The processor’s JTAG interface ensures that the
emulator does not affect target system loading or timing.
For complete information on Analog Devices’ SHARC DSP
Tools product line of JTAG emulator operation, refer to the
appropriate emulator user’s guide.
DEVELOPMENT TOOLS
The processor is supported with a complete set of
CROSSCORE
®† software and hardware development tools,
including Analog Devices emulators and VisualDSP++
®‡ devel-
opment environment. The same emulator hardware that
supports other SHARC processors also fully emulates the
ADSP-2136x processors.
The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy-to-use assembler (based on an algebraic syn-
tax), an archiver (librarian/library builder), a linker, a loader, a
cycle-accurate instruction-level simulator, a C/C++ compiler,
and a C/C++ runtime library that includes DSP and mathemati-
cal functions. A key point for these tools is C/C++ code
efficiency. The compiler has been developed for efficient trans-
lation of C/C++ code to DSP assembly. The SHARC has
architectural features that improve the efficiency of compiled
C/C++ code.
The VisualDSP++ debugger has a number of important fea-
tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa-
tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in com-
plexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity. Sta-
tistical profiling enables the programmer to nonintrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and
efficiently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.
Through debugging both C/C++ and assembly programs with
the VisualDSP++ debugger, programmers can:
• View mixed C/C++ and assembly code (interleaved source
and object information)
• Insert breakpoints
• Set conditional breakpoints on registers, memory,
and stacks
• Perform linear or statistical profiling of program execution
• Fill, dump, and graphically plot the contents of memory
• Perform source level debugging
• Create custom debugger windows
The VisualDSP++ integrated development and debugging envi-
ronment (IDDE) lets programmers define and manage DSP
software development. Its dialog boxes and property pages let
programmers configure and manage all of the SHARC develop-
ment tools, including the color syntax highlighting in the
VisualDSP++ editor. This capability permits programmers to:
• Control how the development tools process inputs and
generate outputs
• Maintain a one-to-one correspondence with the tool’s
command line switches
The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the mem-
ory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
eliminating the need to start from the very beginning, when
developing new application code. The VDK features include
threads, critical and unscheduled regions, semaphores, events,
and device flags. The VDK also supports priority-based, pre-
emptive, cooperative, and time-sliced scheduling approaches. In
addition, the VDK is designed to be scalable. If the application
does not use a specific feature, the support code for that feature
is excluded from the target system.
Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks
and assists in managing system resources, automating the gen-
eration of various VDK-based objects, and visualizing the
system state, when debugging an application that uses the VDK.
Use the expert linker to visually manipulate the placement of
code and data on the embedded system. View memory utiliza-
tion in a color-coded graphical form, easily move code and data
to different areas of the processor or external memory with a
drag of the mouse and examine runtime stack and heap usage.
Figure 3. Analog Power (AVDD) Filter Circuit
CROSSCORE is a registered trademark of Analog Devices, Inc.
VisualDSP++ is a registered trademark of Analog Devices, Inc.
HIGH-Z FERRITE
BEAD CHIP
LOCATE ALL COMPONENTS
CLOSE TO AVDD AND AVSS PINS
AVDD
AVSS
100nF
10nF
1nF
ADSP-213xx
VDDINT


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