PCB Layout Information

In order to obtain the maximum performance from

the AAT4626, very careful attention must be con-

sidered in regard to the printed circuit board layout.

In most port power switch and port protection appli-

cations, high voltage and current transient events

will occur. Proper printed circuit board (PCB) lay-

out can help reduce the effects of transient events.

PCB trace resistance will effect over all circuit tran-

sient response, in addition small voltage drops will

be incurred.

Refer to the following guidelines for power port

PCB layout:

1.

PCB traces should be kept as short and direct

as possible to minimize the effects of the PCB

on circuit performance.

2.

Make component solder pads large to mini-

mize contact resistance

3.

The AAT4626 output bulk capacitors and fer-

rite beads should be placed as close to the

device as possible. PCB traces to the output

connector should be kept as short as possible

to minimized trace resistance and the associ-

ated voltage drop (I2R loss).

4.

If ferrite beads are used in the circuit, select

ferrite beads with a minimum series resistance.

5.

The use of PCB trace vias should be avoided

on all traces that conduct high currents. If

vias are necessary, make the vias as large as

possible and use multiple vias connected in

parallel to minimize their effect.

AAT4626

USB Dual-Channel Power Switch

10

4626.2002.1.0.93

Figure 3: Summary of typical circuit voltage drops caused by AAT4626 circuit components and PCB

trace resistance.

Trace Resistance

0.01ohms

(5mV)

(5mV)

C

BULK

0.1

µF

C

BULK

0.1

µF

Cable, Connector

and Contact

Resistance

0.03ohms

(15mV)

(15mV)

V+

GND

Input

Power Supply

4.50V to 5.25V

P-Channel Mosfet

Switch On Resistance

0.09ohms

(45mV)

AAT4626

Ch. A

Ferrite Bead

and PCB trace

resistance

0.02ohms

(10mV)

(10mV)

GND

Downstream

Peripheral Port

500mA Max.

Load Current

Total Voltage Drop = 75mV

OUTA

IN

GND

Evaluation Board Layout

The AAT4626 evaluation layout follows the recom-

mend printed circuit board layout procedures and

can be used as an example for good application

layouts. Note that ferrite beards are not used on

this simple device evaluation board.

The board

layout shown is not to scale.