TMS27C256 32768 BY 8BIT UV ERASABLE

TMS27PC256 32768 BY 8BIT

PROGRAMMABLE READONLY MEMORIES

SMLS256H− SEPTEMBER 1984 − REVISED NOVEMBER 1997

8

POST OFFICE BOX 1443

switching characteristics over recommended range of operating conditions

PARAMETER

TEST CONDITIONS

(SEE NOTES 3 AND 4)

’27C256-10

’27PC256-10

’27C256-12

’27PC256-12

’27C256-15

’27PC256-15

UNIT

PARAMETER

(SEE NOTES 3 AND 4)

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

ta(A)

Access time from address

100

120

150

ns

ta(E)

Access time from chip enable

C = 100 pF,

100

120

150

ns

ten(G) Output enable time from G

CL = 100 pF,

1 Series 74 TTL Load,

55

55

75

ns

tdis

Output disable time from G or E, whichever

occurs first†

1 Series 74 TTL Load,

Input tr ≤ 20 ns,

Input tf ≤ 20 ns

0

45

0

45

0

60

ns

tv(A)

Output data valid time after change of

address, E, or G, whichever occurs first†

Input tf ≤ 20 ns

0

0

0

ns

PARAMETER

TEST CONDITIONS

(SEE NOTES 3 AND 4)

’27C256-17

’27PC256-17

’27C256-20

’27PC256-20

’27C256-25

’27PC256-25

UNIT

PARAMETER

(SEE NOTES 3 AND 4)

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

ta(A)

Access time from address

170

200

250

ns

ta(E)

Access time from chip enable

C = 100 pF,

170

200

250

ns

ten(G) Output enable time from G

CL = 100 pF,

1 Series 74 TTL Load,

75

75

100

ns

tdis

Output disable time from G or E, whichever

occurs first†

1 Series 74 TTL Load,

Input tr ≤ 20 ns,

Input tf ≤ 20 ns

0

60

0

60

0

60

ns

tv(A)

Output data valid time after change of

address, E, or G, whichever occurs first†

Input tf ≤ 20 ns

0

0

0

ns

† Value calculated from 0.5 V delta to measured level. This parameter is only sampled and not 100% tested.

NOTES:

3. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and

0.8 V for logic low) (see Figure 2).

4. Common test conditions apply for the tdis except during programming.

(see Note 3)

PARAMETER

MIN

MAX

UNIT

tdis(G)

Output disable time from G

0

130

ns

ten(G)

Output enable time from G

150

ns

NOTE 3: For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and

0.8 V for logic low).

timing requirements for programming

MIN

NOM

MAX

UNIT

th(A)

Hold time, address

0

µs

th(D)

Hold time, data

2

µs

tw(IPGM)

Pulse duration, initial program

95

100

105

µs

tsu(A)

Setup time, address

2

µs

tsu(G)

Setup time, G

2

µs

tsu(E)

Setup time, E

2

µs

tsu(D)

Setup time, data

2

µs

tsu(VPP)

Setup time, VPP

2

µs

tsu(VCC)

Setup time, VCC

2

µs