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TLV320AIC10IPFBG4 Datasheet(PDF) 5 Page - Texas Instruments |
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TLV320AIC10IPFBG4 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 57 page  v 5 Parameter Measurement Information 5–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Mechanical Information 6–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix A—Register Set A–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . List of Illustrations Figure Title Page 2–1 Timing Sequence of ADC Channel (Primary Communication Only) 2–1 . . . . . . 2–2 Timing Sequence of ADC Channel (Primary and Secondary Communication) 2–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 Timing Sequence of DAC Channel (Primary Communication Only) 2–3 . . . . . . 2–4 Timing Sequence of DAC Channel (Primary and Secondary Communication) 2–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5 Typical Microphone Interface 2–4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6 Event Monitor Mode Timing 2–5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7 Internal Power-Down Logic 2–6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8 Timing Diagram for the FS Pulse Mode (M1M0 = 00) 2–8 . . . . . . . . . . . . . . . . . . 2–9 Timing Diagram for the SPI_CP0 Mode (M1M0 = 01) 2–8 . . . . . . . . . . . . . . . . . . 2–10 Timing Diagram for the SPI_CP1 Mode (M1M0 = 10) 2–8 . . . . . . . . . . . . . . . . . 2–11 Timing Diagram for the FS Frame Mode (M1M0 = 11) 2–9 . . . . . . . . . . . . . . . . . 2–12 Master Device Frame-Sync Signal With Primary and Secondary Communication ( No Slaves) 2–9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13 Master Device’s FS Output to DSP and FSD Output to the Slave 2–10 . . . . . . . 2–14 Cascade Mode Connection (to DSP Interface) 2–10 . . . . . . . . . . . . . . . . . . . . . . . 2–15 Master-Slave Frame-Sync Timing 2–11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16 INP and INM Internal Self-Biased (AVDD/2) Circuit 2–11 . . . . . . . . . . . . . . . . . . . 2–17 Differential Output Drive (Ground-Referenced) 2–12 . . . . . . . . . . . . . . . . . . . . . . . 2–18 Single-Ended Input 2–12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19 Single-Ended Output 2–12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1 Primary Serial Communication Timing 3–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2 Hardware and Software Secondary Communication Request 3–2 . . . . . . . . . . . 3–3 Device 3/Register 1 Read Operation Timing Diagram 3–3 . . . . . . . . . . . . . . . . . . 3–4 Device 3/Register 1 Write Operation Timing Diagram 3–4 . . . . . . . . . . . . . . . . . . 3–5 FS Output When Hardware Secondary Serial Communication Is Requested Only Once (No Slave) 3–4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6 Output When Hardware Secondary Serial Communication Is Requested (Three Slaves) 3–5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7 FS Output During Software Secondary Serial Communication Request (No Slave) 3–5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8 Direct Configuration 3–6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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