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PALCE16V8H-15SC5 Datasheet(PDF) 4 Page - Advanced Micro Devices |
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PALCE16V8H-15SC5 Datasheet(HTML) 4 Page - Advanced Micro Devices |
4 / 26 page AMD 2-39 PALCE16V8 Family FUNCTIONAL DESCRIPTION The PALCE16V8 is a universal PAL device. It has eight independently configurable macrocells (MC0 –MC7). Each macrocell can be configured as registered output, combinatorial output, combinatorial I/O or dedicated in- put. The programming matrix implements a program- mable AND logic array, which drives a fixed OR logic array. Buffers for device inputs have complementary outputs to provide user-programmable input signal po- larity. Pins 1 and 11 serve either as array inputs or as clock (CLK) and output enable ( OE), respectively, for all flip-flops. Unused input pins should be tied directly to VCC or GND. Product terms with all bits unprogrammed (discon- nected) assume the logical HIGH state and product terms with both true and complement of any input signal connected assume a logical LOW state. The programmable functions on the PALCE16V8 are automatically configured from the user’s design specification. The design specification is processed by development software to verify the design and create a programming file (JEDEC). This file, once downloaded to a programmer, configures the device according to the user’s desired function. The user is given two design options with the PALCE16V8. First, it can be programmed as a standard PAL device from the PAL16R8 and PAL10H8 series. The PAL programmer manufacturer will supply device codes for the standard PAL device architectures to be used with the PALCE16V8. The programmer will pro- gram the PALCE16V8 in the corresponding architec- ture. This allows the user to use existing standard PAL device JEDEC files without making any changes to them. Alternatively, the device can be programmed as a PALCE16V8. Here the user must use the PALCE16V8 device code. This option allows full utilization of the macrocell. 16493D-4 *In macrocells MC0 and MC7 , SG1 is replaced by SG0 on the feedback multiplexer. 1 1 0 X 1 0 SG1 SG1 SL0 X DQ Q 1 0 1 1 0 X 1 1 1 0 0 0 0 1 VCC CLK SL0X OE To Adjacent Macrocell From Adjacent Pin 1 1 0 X 1 0 * SL1X I/OX PALCE16V8 Macrocell |
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