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LP62S2048U-10LLI Datasheet(PDF) 6 Page - AMIC Technology |
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LP62S2048U-10LLI Datasheet(HTML) 6 Page - AMIC Technology |
6 / 17 page LP62S2048-I Series (August, 2001, Version 1.0) 6 AMIC Technology, Inc. AC Characteristics (TA = -40 °C to + 85°C, VCC = 2.7V to 3.3V) Symbol Parameter LP62S2048-70LI/LLI LP62S2048-10LI/LLI Unit Min. Max. Min. Max. Read Cycle tRC Read Cycle Time 70 - 100 - ns tAA Address Access Time - 70 - 100 ns tACE1 Chip Enable Access Time CE1 - 70 - 100 ns tACE2 CE2 - 70 - 100 ns tOE Output Enable to Output Valid - 35 - 50 ns tCLZ1 Chip Enable to Output in Low Z CE1 10 - 10 - ns tCLZ2 CE2 10 - 10 - ns tOLZ Output Enable to Output in Low Z 5 - 5 - ns tCHZ1 Chip Disable to Output in High Z CE1 0 25 0 35 ns tCHZ2 CE2 0 25 0 35 ns tOHZ Output Disable to Output in High Z 0 25 0 35 ns tOH Output Hold from Address Change 10 - 10 - ns Write Cycle tWC Write Cycle Time 70 - 100 - ns tCW Chip Enable to End of Write 60 - 80 - ns tAS Address Setup Time 0 - 0 - ns tAW Address Valid to End of Write 60 - 80 - ns tWP Write Pulse Width 50 - 60 - ns tWR Write Recovery Time 0 - 0 - ns tWHZ Write to Output in High Z 0 25 0 35 ns tDW Data to Write Time Overlap 30 - 40 - ns tDH Data Hold from Write Time 0 - 0 - ns tOW Output Active from End of Write 5 - 5 - ns Notes: tCHZ1, tCHZ2, tOHZ, and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. |
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