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PALCE20V8Q-10JI5 Datasheet(PDF) 1 Page - Advanced Micro Devices |
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PALCE20V8Q-10JI5 Datasheet(HTML) 1 Page - Advanced Micro Devices |
1 / 16 page Publication# 16491 Rev. D Amendment /0 Issue Date: February 1996 2-155 Advanced Micro Devices PALCE20V8 Family EE CMOS 24-Pin Universal Programmable Array Logic FINAL COM’L: H-5/7/10/15/25, Q-10/15/25 IND: H-15/25, Q-20/25 DISTINCTIVE CHARACTERISTICS s Pin and function compatible with all GAL 20V8/As s Electrically erasable CMOS technology pro- vides reconfigurable logic and full testability s High-speed CMOS technology — 5-ns propagation delay for “-5” version — 7.5-ns propagation delay for “-7” version s Direct plug-in replacement for a wide range of 24-pin PAL devices s Programmable enable/disable control s Outputs individually programmable as registered or combinatorial s Peripheral Component Interconnect (PCI) compliant s Preloadable output registers for testability s Automatic register reset on power-up s Cost-effective 24-pin plastic SKINNYDIP and 28-pin PLCC packages s Extensive third-party software and programmer support through FusionPLD partners s Fully tested for 100% programming and func- tional yields and high reliability s Programmable output polarity s 5-ns version utilizes a split leadframe for improved performance GENERAL DESCRIPTION The PALCE20V8 is an advanced PAL device built with low-power, high-speed, electrically-erasable CMOS technology. Its macrocells provide a universal device architecture. The PALCE20V8 is fully compatible with the GAL20V8 and can directly replace PAL20R8 series devices and most 24-pin combinatorial PAL devices. Device logic is automatically configured according to the user’s design specification. A design is implemented using any of a number of popular design software pack- ages, allowing automatic creation of a programming file based on Boolean or state equations. Design software also verifies the design and can provide test vectors for the finished device. Programming can be accomplished on standard PAL device programmers. The PALCE20V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic can always be reduced to sum-of-products form, taking advantage of the very wide input gates available in PAL devices. The equa- tions are programmed into the device through floating- gate cells in the AND logic array that can be erased electrically. The fixed OR array allows up to eight data product terms per output for logic functions. The sum of these products feeds the output macrocell. Each macrocell can be programmed as registered or combinatorial with an active-high or active-low output. The output configura- tion is determined by two global bits and one local bit controlling four multiplexers in each macrocell. 16491D-1 MACRO MACRO MACRO MACRO MACRO MACRO MACRO MACRO MC0 MC7 MC6 MC5 MC4 MC3 MC2 MC1 I1 – I10 CLK/I0 OE/I11 I12 I/O0 I/O1 I/O2 I/O4 I/O4 I/O5 I/O6 I/O7 I13 10 Input Mux. Input Mux. BLOCK DIAGRAM Programmable AND Array 40 x 64 |
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