LP62S1024B-T Series

PRELIMINARY

(October, 2002, Version 0.1)

10

AMIC Technology, Corp.

Timing Waveforms (continued)

Write Cycle 2

(Chip Enable Controlled)

Address

CE1

CE2

(4)

(4)

WE

4. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after

the WE transition, outputs remain in a high impedance state.

7. Transition is measured

±500mV from steady state. This parameter is sampled and not 100% tested.