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LP62S1024AV-70LLI Datasheet(PDF) 1 Page - AMIC Technology |
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LP62S1024AV-70LLI Datasheet(HTML) 1 Page - AMIC Technology |
1 / 15 page LP62S1024A-I Series Preliminary 128K X 8 BIT LOW VOLTAGE CMOS SRAM PRELIMINARY (August, 2001, Version 0.1) 1 AMIC Technology, Inc. Features n Power supply range: 2.7V to 3.6V n Access times: 55/70 ns (max.) n Current: Very low power version: Operating:(70NS)30mA(max.) (55NS)40mA(max.) Standby: 5uA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Output enable and two chip enable inputs for easy application n Data retention voltage: 2V (min.) n Available in 32-pin TSOP, TSSOP (8X13.4mm) packages General Description The LP62S1024A-I is a low operating current 1,048,576- bit static random access memory organized as 131,072 words by 8 bits and operates on a low power voltage: 2.7V to 3.6V. It is built using AMIC's high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Two chip enable inputs are provided for POWER-DOWN and device enable and an output enable input is included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2V. n n TSOP/TSSOP 1 16 17 32 Pin No. Pin Name Pin No. Pin Name 1 2 A9 3 4 5 6 7 8 9 10 11 12 13 14 30 29 28 27 26 25 24 22 19 21 20 23 18 17 A8 A13 CE2 A15 VCC NC I/O8 A16 A14 A12 A7 A6 A3 A2 A1 A0 I/O1 I/O2 GND I/O4 I/O5 I/O6 I/O7 I/O3 A11 WE CE1 15 16 31 32 A5 A4 A10 OE |
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